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5cf8640220
Summary: - Adds E830 device support - Adds pre-release E825C support (for the Ethernet device included in an upcoming Xeon D platform) - Add sysctl for E810 devices to print out PHY debug statistics (mostly for FEC debugging) - Adds per-TX-queue tso counter sysctl to count how many times a TSO offload was requested for a packet, matching other Intel drivers - Various bug fixes Signed-off-by: Eric Joyner <erj@FreeBSD.org> Tested by: Jeffrey Pieper <jeffrey.e.pieper@intel.com> Relnotes: yes Sponsored by: Intel Corporation Differential Revisison: https://reviews.freebsd.org/D46949 (cherry picked from commit f2635e844dd138ac9dfba676f27d41750049af26)
140 lines
4.6 KiB
C
140 lines
4.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/* Copyright (c) 2024, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ICE_CONTROLQ_H_
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#define _ICE_CONTROLQ_H_
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#include "ice_adminq_cmd.h"
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/* Maximum buffer lengths for all control queue types */
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#define ICE_AQ_MAX_BUF_LEN 4096
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#define ICE_MBXQ_MAX_BUF_LEN 4096
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#define ICE_SBQ_MAX_BUF_LEN 512
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#define ICE_CTL_Q_DESC(R, i) \
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(&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
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#define ICE_CTL_Q_DESC_UNUSED(R) \
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((u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
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(R)->next_to_clean - (R)->next_to_use - 1))
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/* Defines that help manage the driver vs FW API checks.
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* Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
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*/
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#define EXP_FW_API_VER_BRANCH_E830 0x00
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#define EXP_FW_API_VER_MAJOR_E830 0x01
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#define EXP_FW_API_VER_MINOR_E830 0x07
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#define EXP_FW_API_VER_BRANCH_E810 0x00
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#define EXP_FW_API_VER_MAJOR_E810 0x01
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#define EXP_FW_API_VER_MINOR_E810 0x05
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#define EXP_FW_API_VER_BRANCH_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? \
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EXP_FW_API_VER_BRANCH_E830 : \
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EXP_FW_API_VER_BRANCH_E810)
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#define EXP_FW_API_VER_MAJOR_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? \
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EXP_FW_API_VER_MAJOR_E830 : \
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EXP_FW_API_VER_MAJOR_E810)
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#define EXP_FW_API_VER_MINOR_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? \
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EXP_FW_API_VER_MINOR_E830 : \
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EXP_FW_API_VER_MINOR_E810)
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/* Different control queue types: These are mainly for SW consumption. */
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enum ice_ctl_q {
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ICE_CTL_Q_UNKNOWN = 0,
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ICE_CTL_Q_ADMIN,
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ICE_CTL_Q_MAILBOX,
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ICE_CTL_Q_SB,
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};
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/* Control Queue timeout settings - max delay 1s */
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#define ICE_CTL_Q_SQ_CMD_TIMEOUT 100000 /* Count 100000 times */
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#define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */
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#define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */
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struct ice_ctl_q_ring {
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void *dma_head; /* Virtual address to DMA head */
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struct ice_dma_mem desc_buf; /* descriptor ring memory */
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union {
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struct ice_dma_mem *sq_bi;
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struct ice_dma_mem *rq_bi;
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} r;
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u16 count; /* Number of descriptors */
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/* used for interrupt processing */
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u16 next_to_use;
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u16 next_to_clean;
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/* used for queue tracking */
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u32 head;
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u32 tail;
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u32 len;
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u32 bah;
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u32 bal;
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u32 len_mask;
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u32 len_ena_mask;
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u32 len_crit_mask;
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u32 head_mask;
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};
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/* sq transaction details */
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struct ice_sq_cd {
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struct ice_aq_desc *wb_desc;
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};
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/* rq event information */
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struct ice_rq_event_info {
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struct ice_aq_desc desc;
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u16 msg_len;
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u16 buf_len;
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u8 *msg_buf;
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};
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/* Control Queue information */
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struct ice_ctl_q_info {
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enum ice_ctl_q qtype;
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struct ice_ctl_q_ring rq; /* receive queue */
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struct ice_ctl_q_ring sq; /* send queue */
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u32 sq_cmd_timeout; /* send queue cmd write back timeout */
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u16 num_rq_entries; /* receive queue depth */
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u16 num_sq_entries; /* send queue depth */
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u16 rq_buf_size; /* receive queue buffer size */
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u16 sq_buf_size; /* send queue buffer size */
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enum ice_aq_err sq_last_status; /* last status on send queue */
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struct ice_lock sq_lock; /* Send queue lock */
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struct ice_lock rq_lock; /* Receive queue lock */
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};
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#endif /* _ICE_CONTROLQ_H_ */
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