Zbigniew Bodek 08d94c6eab Enable HWPMC overflow IRQ on both CPUs in MPIC ... This commit enables usage of HWPMC interrupts for the Marvell SoCs, which use MPIC (Armada38x and ArmadaXP). Those interrupts require extra unmasking, comparing to others. Also, in order to process counters per-CPU, they are masked/unmasked using separate registers' sets for each core. Submitted by: Michal Mazur <mkm@semihalf.com> Marcin Wojtas <mw@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield, Netgate Differential revision: https://reviews.freebsd.org/D10913		2017-06-13 18:55:21 +00:00
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arm	Enable HWPMC overflow IRQ on both CPUs in MPIC	2017-06-13 18:55:21 +00:00
arm64	A64 thermal sensor IRQ is GIC_SPI 31, not 41.	2016-09-04 22:30:46 +00:00
mips	Switch BERI Programmable Interrupt Controller to INTRNG.	2017-04-18 17:20:03 +00:00
powerpc	Make dpaa work with only slightly modified Linux device trees.	2016-11-12 20:45:03 +00:00
riscv	o Update QEMU device tree.	2016-09-07 15:48:44 +00:00
bindings-gpio.txt	Add the missing ')' at end of sentence. Reword it to use a more common	2014-02-05 17:08:55 +00:00
bindings-localbus.txt	Add architecture dependent code to support NAND Framework on Marvell SoCs.	2012-05-18 14:41:14 +00:00
bindings-mpp.txt
Makefile	Add Allwinner A64 (sun50i) and Pine64 dts files.	2016-08-31 16:56:54 +00:00
Makefile.inc	Fix the script to run make_dtb.sh instead of just dtc.	2014-06-07 02:38:13 +00:00