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Add architecture dependent code to support NAND Framework on Marvell SoCs.

Browse source 
Obtained from: Semihalf
Supported by:  FreeBSD Foundation, Juniper Networks
This commit is contained in:
Grzegorz Bernacki 2012-05-18 14:41:14 +00:00
parent 549b307193
commit b91fab4255
14 changed files with 205 additions and 97 deletions
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5
sys/arm/conf/DB-78XXX
View file

@ -17,6 +17,7 @@ options SCHED_4BSD #4BSD scheduler
options INET #InterNETworking
options INET6 #IPv6 communications protocols
options FFS #Berkeley Fast Filesystem
options NANDFS #NAND Filesystem
options NFSCL #New Network Filesystem Client
options NFSLOCKD #Network Lock Manager
options NFS_ROOT #NFS usable as /, requires NFSCL
@ -82,6 +83,10 @@ device ds133x
# SATA
device mvs
# NAND
device nand
# Flattened Device Tree
options FDT
options FDT_DTB_STATIC
makeoptions FDT_DTS_FILE=db78100.dts

5
sys/arm/conf/DB-88F6XXX
View file

@ -17,6 +17,7 @@ options SCHED_4BSD #4BSD scheduler
options INET #InterNETworking
options INET6 #IPv6 communications protocols
options FFS #Berkeley Fast Filesystem
options NANDFS #NAND Filesystem
options NFSCL #New Network Filesystem Client
options NFSLOCKD #Network Lock Manager
options NFS_ROOT #NFS usable as /, requires NFSCL
@ -85,6 +86,10 @@ device iicbus
# SATA
device mvs
# NAND
device nand
# Flattened Device Tree
options FDT
options FDT_DTB_STATIC
makeoptions FDT_DTS_FILE=db88f6281.dts

4
sys/arm/conf/SHEEVAPLUG
View file

@ -17,6 +17,7 @@ options SCHED_4BSD #4BSD scheduler
options INET #InterNETworking
options INET6 #IPv6 communications protocols
options FFS #Berkeley Fast Filesystem
options NANDFS #NAND Filesystem
options NFSCL #New Network Filesystem Client
options NFSLOCKD #Network Lock Manager
options NFS_ROOT #NFS usable as /, requires NFSCL
@ -72,6 +73,9 @@ device scbus
device pass
device da
# NAND
device nand
# Flattened Device Tree
options FDT
options FDT_DTB_STATIC

1
sys/arm/include/fdt.h
View file

@ -57,6 +57,7 @@ struct mem_region {
vm_size_t mr_size;
};
int fdt_localbus_devmap(phandle_t, struct pmap_devmap *, int, int *);
int fdt_pci_devmap(phandle_t, struct pmap_devmap *devmap, vm_offset_t,
vm_offset_t);

24
sys/arm/mv/discovery/discovery.c
View file

@ -43,6 +43,30 @@ __FBSDID("$FreeBSD$");
#include <arm/mv/mvvar.h>
#include <arm/mv/mvwin.h>
/*
* Virtual address space layout:
* -----------------------------
* 0x0000_0000 - 0xBFFF_FFFF : User Process (3 GB)
* 0xC000_0000 - virtual_avail : Kernel Reserved (text, data, page tables,
* : stack etc.)
* virtual-avail - 0xEFFF_FFFF : KVA (virtual_avail is typically < 0xc0a0_0000)
* 0xF000_0000 - 0xF0FF_FFFF : No-Cache allocation area (16 MB)
* 0xF100_0000 - 0xF10F_FFFF : SoC Integrated devices registers range (1 MB)
* 0xF110_0000 - 0xF11F_FFFF : PCI-Express I/O space (1MB)
* 0xF120_0000 - 0xF12F_FFFF : PCI I/O space (1MB)
* 0xF130_0000 - 0xF52F_FFFF : PCI-Express memory space (64MB)
* 0xF530_0000 - 0xF92F_FFFF : PCI memory space (64MB)
* 0xF930_0000 - 0xF93F_FFFF : Device Bus: BOOT (1 MB)
* 0xF940_0000 - 0xF94F_FFFF : Device Bus: CS0 (1 MB)
* 0xF950_0000 - 0xFB4F_FFFF : Device Bus: CS1 (32 MB)
* 0xFB50_0000 - 0xFB5F_FFFF : Device Bus: CS2 (1 MB)
* 0xFB60_0000 - 0xFFFE_FFFF : Unused (~74MB)
* 0xFFFF_0000 - 0xFFFF_0FFF : 'High' vectors page (4 kB)
* 0xFFFF_1000 - 0xFFFF_1FFF : ARM_TP_ADDRESS/RAS page (4 kB)
* 0xFFFF_2000 - 0xFFFF_FFFF : Unused (56 kB)
*/
struct resource_spec mv_gpio_res[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ SYS_RES_IRQ, 0, RF_ACTIVE },

2
sys/arm/mv/files.mv
View file

@ -22,6 +22,7 @@ arm/mv/bus_space.c standard
arm/mv/common.c standard
arm/mv/gpio.c standard
arm/mv/ic.c standard
arm/mv/mv_localbus.c standard
arm/mv/mv_machdep.c standard
arm/mv/mv_pci.c optional pci
arm/mv/mv_sata.c optional ata | atamvsata
@ -30,6 +31,7 @@ arm/mv/twsi.c optional iicbus
dev/cesa/cesa.c optional cesa
dev/mge/if_mge.c optional mge
dev/nand/nfc_mv.c optional nand
dev/mvs/mvs_soc.c optional mvs
dev/uart/uart_dev_ns8250.c optional uart
dev/usb/controller/ehci_mv.c optional ehci

57
sys/arm/mv/mv_machdep.c
View file

@ -314,7 +314,7 @@ initarm(void *mdp, void *unused __unused)
uint32_t memsize, l2size;
void *kmdp;
u_int l1pagetable;
int i = 0, j = 0;
int i = 0, j = 0, err_devmap = 0;
kmdp = NULL;
lastaddr = 0;
@ -496,8 +496,7 @@ initarm(void *mdp, void *unused __unused)
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
/* Map pmap_devmap[] entries */
if (platform_devmap_init() != 0)
while (1);
err_devmap = platform_devmap_init();
pmap_devmap_bootstrap(l1pagetable, pmap_devmap_bootstrap_table);
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
@ -530,12 +529,17 @@ initarm(void *mdp, void *unused __unused)
print_kernel_section_addr();
print_kenv();
if (err_devmap != 0)
printf("WARNING: could not fully configure devmap, error=%d\n",
err_devmap);
/*
* Re-initialise decode windows
*/
if (soc_decode_win() != 0)
printf("WARNING: could not re-initialise decode windows! "
"Running with existing settings...\n");
/*
* Pages were allocated during the secondary bootstrap for the
* stacks for different CPU modes.
@ -733,25 +737,34 @@ moveon:
return (0);
}
#define FDT_DEVMAP_MAX (1 + 2 + 1 + 1)
#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 1)
static struct pmap_devmap fdt_devmap[FDT_DEVMAP_MAX] = {
{ 0, 0, 0, 0, 0, }
};
/*
* XXX: When device entry in devmap has pd_size smaller than section size,
* system will freeze during initialization
*/
/*
* Construct pmap_devmap[] with DT-derived config data.
*/
static int
platform_devmap_init(void)
{
phandle_t root, child;
pcell_t bank_count;
u_long base, size;
int i;
int i, num_mapped;
i = 0;
pmap_devmap_bootstrap_table = &fdt_devmap[0];
/*
* IMMR range.
*/
i = 0;
fdt_devmap[i].pd_va = fdt_immr_va;
fdt_devmap[i].pd_pa = fdt_immr_pa;
fdt_devmap[i].pd_size = fdt_immr_size;
@ -760,12 +773,12 @@ platform_devmap_init(void)
i++;
/*
* PCI range(s).
* PCI range(s) and localbus.
*/
if ((root = OF_finddevice("/")) == -1)
return (ENXIO);
for (child = OF_child(root); child != 0; child = OF_peer(child))
for (child = OF_child(root); child != 0; child = OF_peer(child)) {
if (fdt_is_type(child, "pci")) {
/*
* Check space: each PCI node will consume 2 devmap
@ -773,7 +786,6 @@ platform_devmap_init(void)
*/
if (i + 1 >= FDT_DEVMAP_MAX) {
return (ENOMEM);
break;
}
/*
@ -786,6 +798,29 @@ platform_devmap_init(void)
i += 2;
}
if (fdt_is_compatible(child, "mrvl,lbc")) {
/* Check available space */
if (OF_getprop(child, "bank-count", (void *)&bank_count,
sizeof(bank_count)) <= 0)
/* If no property, use default value */
bank_count = 1;
else
bank_count = fdt32_to_cpu(bank_count);
if ((i + bank_count) >= FDT_DEVMAP_MAX)
return (ENOMEM);
/* Add all localbus ranges to device map */
num_mapped = 0;
if (fdt_localbus_devmap(child, &fdt_devmap[i],
(int)bank_count, &num_mapped) != 0)
return (ENXIO);
i += num_mapped;
}
}
/*
* CESA SRAM range.
*/
@ -795,7 +830,7 @@ platform_devmap_init(void)
if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0)
/* No CESA SRAM node. */
goto out;
return (0);
moveon:
if (i >= FDT_DEVMAP_MAX)
return (ENOMEM);
@ -809,8 +844,6 @@ moveon:
fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
fdt_devmap[i].pd_cache = PTE_NOCACHE;
out:
pmap_devmap_bootstrap_table = &fdt_devmap[0];
return (0);
}

25
sys/arm/mv/mvwin.h
View file

@ -57,20 +57,17 @@
#define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE
#define MV_PCI_MEM_SIZE (64 * 1024 * 1024)
/* XXX DEV_BOOT, CSx are board specific, should be defined per platform */
#define MV_DEV_BOOT_BASE 0xF9300000
#define MV_DEV_BOOT_SIZE (1024 * 1024) /* 1 MB */
/* 512KB NOR FLASH */
#define MV_DEV_BOOT_PHYS_BASE (MV_PCI_MEM_PHYS_BASE + MV_PCI_MEM_SIZE)
#define MV_DEV_BOOT_SIZE (512 * 1024)
/* CS0: 7-seg LED */
#define MV_DEV_CS0_PHYS_BASE 0xFA000000
#define MV_DEV_CS0_SIZE (1024 * 1024) /* XXX u-boot has 2MB */
/* CS1: 32MB NOR FLASH */
#define MV_DEV_CS1_PHYS_BASE (MV_DEV_CS0_PHYS_BASE + MV_DEV_CS0_SIZE)
#define MV_DEV_CS1_SIZE (32 * 1024 * 1024)
/* CS2: 32MB NAND FLASH */
#define MV_DEV_CS2_PHYS_BASE (MV_DEV_CS1_PHYS_BASE + MV_DEV_CS1_SIZE)
#define MV_DEV_CS2_SIZE 1024 /* XXX u-boot has 1MB */
#define MV_DEV_CS0_BASE 0xF9400000
#define MV_DEV_CS0_SIZE (1024 * 1024) /* 1 MB */
#define MV_DEV_CS1_BASE 0xF9500000
#define MV_DEV_CS1_SIZE (32 * 1024 * 1024) /* 32 MB */
#define MV_DEV_CS2_BASE 0xFB500000
#define MV_DEV_CS2_SIZE (1024 * 1024) /* 1 MB */
#define MV_CESA_SRAM_PHYS_BASE 0xFD000000
#define MV_CESA_SRAM_BASE MV_CESA_SRAM_PHYS_BASE /* VA == PA mapping */
@ -107,8 +104,6 @@
#define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000)
#define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000)
#define MV_DEV_CS0_BASE MV_DEV_CS0_PHYS_BASE
/*
* Decode windows definitions and macros
*/

83
sys/boot/fdt/dts/bindings-localbus.txt Normal file
View file

@ -0,0 +1,83 @@
$FreeBSD$
Marvell Device bus (localbus) configuration.
============================================
1. Properties for localbus nodes
1.1 ranges
Property: ranges
Value type: <prop-encoded-array> encoded as arbitrary number of localbus
nodes specifiers.
Description: ranges property defines values used for mapping devices
connected to localbus, in Marvell devices it is used also for
setting decoding windows.
a) child node address-cells:
- first cell: number of bank (chip select)
- second cell: (Marvell devices) Target ID for decoding
windows setup
b) parent node address cells:
- address offset: used with parent's node base address to
specify base address of mapped device
c) child node size-cells:
- size: defines amount of memory that should be reserved for
device
1.2 bank-count
Property: bank-count
Value type: <u32>
Description: The bank_count property defines maximum number of banks on
localbus node. Bank is most often interpreted as device chip
select, but may also describe another device (e.g. SPI flash).
1.3 Example
localbus@0 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "mrvl,lbc";
bank-count = <5>;
/* This reflects CPU decode windows setup. */
ranges = <0x0 0x2f 0xb2200000 0x00100000
0x1 0x3e 0xb2100000 0x00100000
0x2 0x3d 0xb0000000 0x02000000
0x3 0x3b 0xb2000000 0x00100000>;
};
2. Properties for localbus consumer nodes:
2.1 reg
Property: reg
Value type: <prop-encoded-array>
Description: A standard property required for localbus child nodes. Defines
the device memory region.
a) first cell: number of bank (chip select)
b) address offset: used with address offset from parent's ranges
for corresponding bank to specify base address of
the device
c) size: defines size of the device memory region
2.2 Example
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x00100000>;
};

19
sys/boot/fdt/dts/db78100.dts
View file

@ -69,25 +69,23 @@
reg = <0x0 0x20000000>; // 512M at 0x0
};
localbus@f1000000 {
localbus@0 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "mrvl,lbc";
win-count = <14>;
bank-count = <5>;
/* This reflects CPU decode windows setup. */
ranges = <0x0 0x0f 0xf9300000 0x00100000
0x1 0x1e 0xfa000000 0x00100000
0x2 0x1d 0xfa100000 0x02000000
0x3 0x1b 0xfc100000 0x00000400>;
ranges = <0x0 0x2f 0xf9300000 0x00100000
0x1 0x3e 0xf9400000 0x00100000
0x2 0x3d 0xf9500000 0x02000000
0x3 0x3b 0xfb500000 0x00100000>;
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x00100000>;
bank-width = <2>;
device-width = <1>;
};
led@1,0 {
@ -102,16 +100,13 @@
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x2 0x0 0x02000000>;
bank-width = <2>;
device-width = <1>;
};
nand@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mrvl,nfc";
reg = <0x3 0x0 0x00100000>;
bank-width = <2>;
device-width = <1>;
};
};

39
sys/boot/fdt/dts/db88f6281.dts
View file

@ -72,48 +72,24 @@
reg = <0x0 0x20000000>; // 512M at 0x0
};
localbus@f1000000 {
localbus@0 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "mrvl,lbc";
bank-count = <3>;
/* This reflects CPU decode windows setup. */
ranges = <0x0 0x0f 0xf9300000 0x00100000
0x1 0x1e 0xfa000000 0x00100000
0x2 0x1d 0xfa100000 0x02000000
0x3 0x1b 0xfc100000 0x00000400>;
ranges = <0x0 0x2f 0xf9300000 0x00100000>;
nor@0,0 {
nand@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
compatible = "mrvl,nfc";
reg = <0x0 0x0 0x00100000>;
bank-width = <2>;
device-width = <1>;
};
led@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "led";
reg = <0x1 0x0 0x00100000>;
};
nor@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x2 0x0 0x02000000>;
bank-width = <2>;
device-width = <1>;
};
nand@3,0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x3 0x0 0x00100000>;
bank-width = <2>;
device-width = <1>;
};
};
@ -305,4 +281,9 @@
0x0 0x00100000>;
};
};
chosen {
stdin = "serial0";
stdout = "serial0";
};
};

34
sys/boot/fdt/dts/sheevaplug.dts
View file

@ -71,48 +71,24 @@
reg = <0x0 0x20000000>; // 512M at 0x0
};
localbus@f1000000 {
localbus@0 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "mrvl,lbc";
bank-count = <3>;
/* This reflects CPU decode windows setup. */
ranges = <0x0 0x0f 0xf9300000 0x00100000
0x1 0x1e 0xfa000000 0x00100000
0x2 0x1d 0xfa100000 0x02000000
0x3 0x1b 0xfc100000 0x00000400>;
ranges = <0x0 0x2f 0xf9300000 0x00100000>;
nor@0,0 {
nand@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
compatible = "mrvl,nfc";
reg = <0x0 0x0 0x00100000>;
bank-width = <2>;
device-width = <1>;
};
led@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "led";
reg = <0x1 0x0 0x00100000>;
};
nor@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x2 0x0 0x02000000>;
bank-width = <2>;
device-width = <1>;
};
nand@3,0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x3 0x0 0x00100000>;
bank-width = <2>;
device-width = <1>;
};
};

1
sys/boot/uboot/lib/api_public.h
View file

@ -132,6 +132,7 @@ typedef unsigned long lbastart_t;
#define DT_STOR_SCSI 0x0020
#define DT_STOR_USB 0x0040
#define DT_STOR_MMC 0x0080
#define DT_STOR_NAND 0x0100
#define DEV_STA_CLOSED 0x0000 /* invalid, closed */
#define DEV_STA_OPEN 0x0001 /* open i.e. active */

3
sys/boot/uboot/lib/glue.c
View file

@ -407,6 +407,9 @@ ub_stor_type(int type)
if (type & DT_STOR_MMC)
return ("MMC");
if (type & DT_STOR_NAND)
return ("NAND");
return ("Unknown");
}