mirror of
https://github.com/opnsense/src.git
synced 2026-06-08 16:22:46 -04:00
def59b6038
This is part 1 of the support for the new Intel Ethernet E610 family of devices.
Introduce new PCI device IDs:
• 57AE: Intel(R) E610 (Backplane)
• 57AF: Intel(R) E610 (SFP)
• 57B0: Intel(R) E610 (10 GbE)
• 57B1: Intel(R) E610 (2.5 GbE)
• 57B2: Intel(R) E610 (SGMII)
Key updates for E610 family:
• Firmware manages Link and PHY
• Implement new CSR-based Admin Command Interface (ACI) for SW-FW interaction
• Tested exclusively for x64 operating systems on E610-XT2/XT4 (10G) and E610-IT4 (2.5G)
• Enable link speeds above 1G: 2.5G, 5G and 10G
• NVM Recovery Mode and Rollback support
Signed-off-by: Yogesh Bhosale yogesh.bhosale@intel.com
Co-developed-by: Krzysztof Galazka krzysztof.galazka@intel.com
Approved by: kbowling (mentor), erj (mentor)
Tested by: gowtham.kumar.ks_intel.com
Sponsored by: Intel Corporation
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D50067
(cherry picked from commit dea5f973d0)
142 lines
4 KiB
C
142 lines
4 KiB
C
/******************************************************************************
|
|
|
|
Copyright (c) 2001-2020, Intel Corporation
|
|
All rights reserved.
|
|
|
|
Redistribution and use in source and binary forms, with or without
|
|
modification, are permitted provided that the following conditions are met:
|
|
|
|
1. Redistributions of source code must retain the above copyright notice,
|
|
this list of conditions and the following disclaimer.
|
|
|
|
2. Redistributions in binary form must reproduce the above copyright
|
|
notice, this list of conditions and the following disclaimer in the
|
|
documentation and/or other materials provided with the distribution.
|
|
|
|
3. Neither the name of the Intel Corporation nor the names of its
|
|
contributors may be used to endorse or promote products derived from
|
|
this software without specific prior written permission.
|
|
|
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
******************************************************************************/
|
|
|
|
#include "ixgbe.h"
|
|
|
|
inline device_t
|
|
ixgbe_dev_from_hw(struct ixgbe_hw *hw)
|
|
{
|
|
return ((struct ixgbe_softc *)hw->back)->dev;
|
|
}
|
|
|
|
inline u16
|
|
ixgbe_read_pci_cfg(struct ixgbe_hw *hw, u32 reg)
|
|
{
|
|
return pci_read_config(((struct ixgbe_softc *)hw->back)->dev, reg, 2);
|
|
}
|
|
|
|
inline void
|
|
ixgbe_write_pci_cfg(struct ixgbe_hw *hw, u32 reg, u16 value)
|
|
{
|
|
pci_write_config(((struct ixgbe_softc *)hw->back)->dev, reg, value, 2);
|
|
}
|
|
|
|
inline u32
|
|
ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
|
|
{
|
|
return bus_space_read_4(((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_tag,
|
|
((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle, reg);
|
|
}
|
|
|
|
inline void
|
|
ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 val)
|
|
{
|
|
bus_space_write_4(((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_tag,
|
|
((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle,
|
|
reg, val);
|
|
}
|
|
|
|
inline u32
|
|
ixgbe_read_reg_array(struct ixgbe_hw *hw, u32 reg, u32 offset)
|
|
{
|
|
return bus_space_read_4(((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_tag,
|
|
((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle,
|
|
reg + (offset << 2));
|
|
}
|
|
|
|
inline void
|
|
ixgbe_write_reg_array(struct ixgbe_hw *hw, u32 reg, u32 offset, u32 val)
|
|
{
|
|
bus_space_write_4(((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_tag,
|
|
((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle,
|
|
reg + (offset << 2), val);
|
|
}
|
|
|
|
uint64_t
|
|
ixgbe_link_speed_to_baudrate(ixgbe_link_speed speed)
|
|
{
|
|
uint64_t baudrate;
|
|
|
|
switch (speed) {
|
|
case IXGBE_LINK_SPEED_10GB_FULL:
|
|
baudrate = IF_Gbps(10);
|
|
break;
|
|
case IXGBE_LINK_SPEED_5GB_FULL:
|
|
baudrate = IF_Gbps(5);
|
|
break;
|
|
case IXGBE_LINK_SPEED_2_5GB_FULL:
|
|
baudrate = IF_Mbps(2500);
|
|
break;
|
|
case IXGBE_LINK_SPEED_1GB_FULL:
|
|
baudrate = IF_Gbps(1);
|
|
break;
|
|
case IXGBE_LINK_SPEED_100_FULL:
|
|
baudrate = IF_Mbps(100);
|
|
break;
|
|
case IXGBE_LINK_SPEED_10_FULL:
|
|
baudrate = IF_Mbps(10);
|
|
break;
|
|
case IXGBE_LINK_SPEED_UNKNOWN:
|
|
default:
|
|
baudrate = 0;
|
|
break;
|
|
}
|
|
|
|
return baudrate;
|
|
}
|
|
|
|
void
|
|
ixgbe_init_lock(struct ixgbe_lock *lock)
|
|
{
|
|
mtx_init(&lock->mutex, "mutex",
|
|
"ixgbe ACI lock", MTX_DEF | MTX_DUPOK);
|
|
}
|
|
|
|
void
|
|
ixgbe_acquire_lock(struct ixgbe_lock *lock)
|
|
{
|
|
mtx_lock(&lock->mutex);
|
|
}
|
|
|
|
void
|
|
ixgbe_release_lock(struct ixgbe_lock *lock)
|
|
{
|
|
mtx_unlock(&lock->mutex);
|
|
}
|
|
|
|
void
|
|
ixgbe_destroy_lock(struct ixgbe_lock *lock)
|
|
{
|
|
if (mtx_initialized(&lock->mutex))
|
|
mtx_destroy(&lock->mutex);
|
|
}
|