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ix/ixv: Add support for new Intel Ethernet E610 family devices
This is part 1 of the support for the new Intel Ethernet E610 family of devices. Introduce new PCI device IDs: • 57AE: Intel(R) E610 (Backplane) • 57AF: Intel(R) E610 (SFP) • 57B0: Intel(R) E610 (10 GbE) • 57B1: Intel(R) E610 (2.5 GbE) • 57B2: Intel(R) E610 (SGMII) Key updates for E610 family: • Firmware manages Link and PHY • Implement new CSR-based Admin Command Interface (ACI) for SW-FW interaction • Tested exclusively for x64 operating systems on E610-XT2/XT4 (10G) and E610-IT4 (2.5G) • Enable link speeds above 1G: 2.5G, 5G and 10G • NVM Recovery Mode and Rollback support Signed-off-by: Yogesh Bhosale yogesh.bhosale@intel.com Co-developed-by: Krzysztof Galazka krzysztof.galazka@intel.com Approved by: kbowling (mentor), erj (mentor) Tested by: gowtham.kumar.ks_intel.com Sponsored by: Intel Corporation MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D50067 (cherry picked from commit dea5f973d0c8d29a79b433283d0a2de8f4615957)
This commit is contained in:
Bhosale, Yogeshnull
Franco Fichtner
parent
aa1fce8528
commit
def59b6038
16 changed files with 8458 additions and 36 deletions
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@ -2300,6 +2300,8 @@ dev/ixgbe/ixgbe_x540.c optional ix inet | ixv inet \
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compile-with "${NORMAL_C} -I$S/dev/ixgbe"
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dev/ixgbe/ixgbe_x550.c optional ix inet | ixv inet \
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compile-with "${NORMAL_C} -I$S/dev/ixgbe"
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dev/ixgbe/ixgbe_e610.c optional ix inet | ixv inet \
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compile-with "${NORMAL_C} -I$S/dev/ixgbe"
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dev/ixgbe/ixgbe_dcb.c optional ix inet | ixv inet \
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compile-with "${NORMAL_C} -I$S/dev/ixgbe"
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dev/ixgbe/ixgbe_dcb_82598.c optional ix inet | ixv inet \
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@ -45,7 +45,7 @@
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/************************************************************************
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* Driver version
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************************************************************************/
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static const char ixgbe_driver_version[] = "4.0.1-k";
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static const char ixgbe_driver_version[] = "5.0.1-k";
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/************************************************************************
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* PCI Device ID Table
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@ -144,6 +144,16 @@ static const pci_vendor_info_t ixgbe_vendor_info_array[] =
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"Intel(R) X540-T2 (Bypass)"),
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PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS,
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"Intel(R) X520 82599 (Bypass)"),
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PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_BACKPLANE,
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"Intel(R) E610 (Backplane)"),
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PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_SFP,
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"Intel(R) E610 (SFP)"),
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PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_2_5G_T,
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"Intel(R) E610 (2.5 GbE)"),
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PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_10G_T,
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"Intel(R) E610 (10 GbE)"),
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PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_SGMII,
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"Intel(R) E610 (SGMII)"),
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/* required last entry */
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PVID_END
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};
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@ -254,6 +264,10 @@ static int ixgbe_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS);
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static void ixgbe_handle_msf(void *);
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static void ixgbe_handle_mod(void *);
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static void ixgbe_handle_phy(void *);
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static void ixgbe_handle_fw_event(void *);
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static int ixgbe_enable_lse(struct ixgbe_softc *sc);
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static int ixgbe_disable_lse(struct ixgbe_softc *sc);
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/************************************************************************
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* FreeBSD Device Interface Entry Points
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@ -622,6 +636,7 @@ ixgbe_initialize_rss_mapping(struct ixgbe_softc *sc)
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case ixgbe_mac_X550:
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case ixgbe_mac_X550EM_x:
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case ixgbe_mac_X550EM_a:
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case ixgbe_mac_E610:
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table_size = 512;
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break;
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default:
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@ -903,6 +918,32 @@ ixgbe_initialize_transmit_units(if_ctx_t ctx)
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} /* ixgbe_initialize_transmit_units */
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static int
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ixgbe_check_fw_api_version(struct ixgbe_softc *sc)
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{
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struct ixgbe_hw *hw = &sc->hw;
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if (hw->api_maj_ver > IXGBE_FW_API_VER_MAJOR) {
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device_printf(sc->dev,
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"The driver for the device stopped because the NVM "
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"image is newer than expected. You must install the "
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"most recent version of the network driver.\n");
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return (EOPNOTSUPP);
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} else if (hw->api_maj_ver == IXGBE_FW_API_VER_MAJOR &&
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hw->api_min_ver > (IXGBE_FW_API_VER_MINOR + 2)) {
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device_printf(sc->dev,
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"The driver for the device detected a newer version of "
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"the NVM image than expected. Please install the most "
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"recent version of the network driver.\n");
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} else if (hw->api_maj_ver < IXGBE_FW_API_VER_MAJOR ||
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hw->api_min_ver < IXGBE_FW_API_VER_MINOR - 2) {
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device_printf(sc->dev,
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"The driver for the device detected an older version "
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"of the NVM image than expected. "
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"Please update the NVM image.\n");
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}
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return (0);
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}
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/************************************************************************
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* ixgbe_register
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************************************************************************/
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@ -971,6 +1012,9 @@ ixgbe_if_attach_pre(if_ctx_t ctx)
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goto err_pci;
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}
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if (hw->mac.type == ixgbe_mac_E610)
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ixgbe_init_aci(hw);
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if (hw->mac.ops.fw_recovery_mode &&
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hw->mac.ops.fw_recovery_mode(hw)) {
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device_printf(dev,
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@ -1059,6 +1103,12 @@ ixgbe_if_attach_pre(if_ctx_t ctx)
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break;
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}
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/* Check the FW API version */
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if (hw->mac.type == ixgbe_mac_E610 && ixgbe_check_fw_api_version(sc)) {
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error = EIO;
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goto err_pci;
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}
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/* Most of the iflib initialization... */
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iflib_set_mac(ctx, hw->mac.addr);
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@ -1112,6 +1162,9 @@ err_pci:
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IXGBE_WRITE_REG(&sc->hw, IXGBE_CTRL_EXT, ctrl_ext);
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ixgbe_free_pci_resources(ctx);
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if (hw->mac.type == ixgbe_mac_E610)
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ixgbe_shutdown_aci(hw);
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return (error);
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} /* ixgbe_if_attach_pre */
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@ -1365,6 +1418,10 @@ ixgbe_add_media_types(if_ctx_t ctx)
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/* Media types with matching FreeBSD media defines */
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if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_T)
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ifmedia_add(sc->media, IFM_ETHER | IFM_10G_T, 0, NULL);
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if (layer & IXGBE_PHYSICAL_LAYER_5000BASE_T)
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ifmedia_add(sc->media, IFM_ETHER | IFM_5000_T, 0, NULL);
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if (layer & IXGBE_PHYSICAL_LAYER_2500BASE_T)
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ifmedia_add(sc->media, IFM_ETHER | IFM_2500_T, 0, NULL);
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if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_T)
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ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
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if (layer & IXGBE_PHYSICAL_LAYER_100BASE_TX)
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@ -1466,6 +1523,7 @@ ixgbe_is_sfp(struct ixgbe_hw *hw)
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}
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case ixgbe_mac_X550EM_x:
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case ixgbe_mac_X550EM_a:
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case ixgbe_mac_E610:
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if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
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return (true);
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return (false);
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@ -1532,6 +1590,15 @@ ixgbe_config_link(if_ctx_t ctx)
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IXGBE_LINK_SPEED_5GB_FULL);
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}
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if (hw->mac.type == ixgbe_mac_E610) {
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hw->phy.ops.init(hw);
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err = ixgbe_enable_lse(sc);
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if (err)
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device_printf(sc->dev,
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"Failed to enable Link Status Event, "
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"error: %d", err);
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}
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if (hw->mac.ops.setup_link)
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err = hw->mac.ops.setup_link(hw, autoneg,
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sc->link_up);
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@ -2165,14 +2232,15 @@ get_parent_info:
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ixgbe_set_pci_config_data_generic(hw, link);
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display:
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device_printf(dev, "PCI Express Bus: Speed %s %s\n",
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((hw->bus.speed == ixgbe_bus_speed_8000) ? "8.0GT/s" :
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device_printf(dev, "PCI Express Bus: Speed %s Width %s\n",
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((hw->bus.speed == ixgbe_bus_speed_16000) ? "16.0GT/s" :
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(hw->bus.speed == ixgbe_bus_speed_8000) ? "8.0GT/s" :
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(hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0GT/s" :
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(hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5GT/s" :
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"Unknown"),
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((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
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(hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
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(hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
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((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "x8" :
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(hw->bus.width == ixgbe_bus_width_pcie_x4) ? "x4" :
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(hw->bus.width == ixgbe_bus_width_pcie_x1) ? "x1" :
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"Unknown"));
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if (bus_info_valid) {
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@ -2379,14 +2447,17 @@ ixgbe_if_media_status(if_ctx_t ctx, struct ifmediareq * ifmr)
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ifmr->ifm_status |= IFM_ACTIVE;
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layer = sc->phy_layer;
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if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_T ||
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layer & IXGBE_PHYSICAL_LAYER_1000BASE_T ||
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layer & IXGBE_PHYSICAL_LAYER_100BASE_TX ||
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layer & IXGBE_PHYSICAL_LAYER_10BASE_T)
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if (layer & IXGBE_PHYSICAL_LAYERS_BASE_T_ALL)
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switch (sc->link_speed) {
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case IXGBE_LINK_SPEED_10GB_FULL:
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ifmr->ifm_active |= IFM_10G_T | IFM_FDX;
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break;
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case IXGBE_LINK_SPEED_5GB_FULL:
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ifmr->ifm_active |= IFM_5000_T | IFM_FDX;
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break;
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case IXGBE_LINK_SPEED_2_5GB_FULL:
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ifmr->ifm_active |= IFM_2500_T | IFM_FDX;
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break;
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case IXGBE_LINK_SPEED_1GB_FULL:
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ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
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break;
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@ -2397,15 +2468,6 @@ ixgbe_if_media_status(if_ctx_t ctx, struct ifmediareq * ifmr)
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ifmr->ifm_active |= IFM_10_T | IFM_FDX;
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break;
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}
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if (hw->mac.type == ixgbe_mac_X550)
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switch (sc->link_speed) {
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case IXGBE_LINK_SPEED_5GB_FULL:
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ifmr->ifm_active |= IFM_5000_T | IFM_FDX;
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break;
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case IXGBE_LINK_SPEED_2_5GB_FULL:
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ifmr->ifm_active |= IFM_2500_T | IFM_FDX;
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break;
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}
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if (layer & IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU ||
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layer & IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA)
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switch (sc->link_speed) {
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@ -2683,6 +2745,11 @@ ixgbe_msix_link(void *arg)
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sc->task_requests |= IXGBE_REQUEST_TASK_LSC;
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}
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if (eicr & IXGBE_EICR_FW_EVENT) {
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IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EICR_FW_EVENT);
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sc->task_requests |= IXGBE_REQUEST_TASK_FWEVENT;
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}
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if (sc->hw.mac.type != ixgbe_mac_82598EB) {
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if ((sc->feat_en & IXGBE_FEATURE_FDIR) &&
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(eicr & IXGBE_EICR_FLOW_DIR)) {
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@ -2741,11 +2808,16 @@ ixgbe_msix_link(void *arg)
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/* Check for VF message */
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if ((sc->feat_en & IXGBE_FEATURE_SRIOV) &&
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(eicr & IXGBE_EICR_MAILBOX))
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(eicr & IXGBE_EICR_MAILBOX)) {
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sc->task_requests |= IXGBE_REQUEST_TASK_MBX;
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}
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}
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if (ixgbe_is_sfp(hw)) {
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/*
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* On E610, the firmware handles PHY configuration, so
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* there is no need to perform any SFP-specific tasks.
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*/
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if (hw->mac.type != ixgbe_mac_E610 && ixgbe_is_sfp(hw)) {
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/* Pluggable optics-related interrupt */
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if (hw->mac.type >= ixgbe_mac_X540)
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eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
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@ -2992,7 +3064,13 @@ ixgbe_if_detach(if_ctx_t ctx)
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callout_drain(&sc->fw_mode_timer);
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if (sc->hw.mac.type == ixgbe_mac_E610) {
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ixgbe_disable_lse(sc);
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ixgbe_shutdown_aci(&sc->hw);
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}
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ixgbe_free_pci_resources(ctx);
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free(sc->mta, M_IXGBE);
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return (0);
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@ -3411,6 +3489,7 @@ ixgbe_set_ivar(struct ixgbe_softc *sc, u8 entry, u8 vector, s8 type)
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case ixgbe_mac_X550:
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case ixgbe_mac_X550EM_x:
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case ixgbe_mac_X550EM_a:
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case ixgbe_mac_E610:
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if (type == -1) { /* MISC IVAR */
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index = (entry & 1) * 8;
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ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
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@ -3832,6 +3911,96 @@ ixgbe_handle_phy(void *context)
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"Error handling LASI interrupt: %d\n", error);
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} /* ixgbe_handle_phy */
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/************************************************************************
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* ixgbe_enable_lse - enable link status events
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*
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* Sets mask and enables link status events
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************************************************************************/
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s32 ixgbe_enable_lse(struct ixgbe_softc *sc)
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{
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s32 error;
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u16 mask = ~((u16)(IXGBE_ACI_LINK_EVENT_UPDOWN |
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IXGBE_ACI_LINK_EVENT_MEDIA_NA |
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IXGBE_ACI_LINK_EVENT_MODULE_QUAL_FAIL |
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IXGBE_ACI_LINK_EVENT_PHY_FW_LOAD_FAIL));
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error = ixgbe_configure_lse(&sc->hw, TRUE, mask);
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if (error)
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return (error);
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sc->lse_mask = mask;
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return (IXGBE_SUCCESS);
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} /* ixgbe_enable_lse */
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/************************************************************************
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* ixgbe_disable_lse - disable link status events
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************************************************************************/
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s32 ixgbe_disable_lse(struct ixgbe_softc *sc)
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{
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s32 error;
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error = ixgbe_configure_lse(&sc->hw, false, sc->lse_mask);
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if (error)
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return (error);
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sc->lse_mask = 0;
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return (IXGBE_SUCCESS);
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} /* ixgbe_disable_lse */
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/************************************************************************
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* ixgbe_handle_fw_event - Tasklet for MSI-X Link Status Event interrupts
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************************************************************************/
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static void
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ixgbe_handle_fw_event(void *context)
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{
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if_ctx_t ctx = context;
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struct ixgbe_softc *sc = iflib_get_softc(ctx);
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struct ixgbe_hw *hw = &sc->hw;
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struct ixgbe_aci_event event;
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bool pending = false;
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s32 error;
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event.buf_len = IXGBE_ACI_MAX_BUFFER_SIZE;
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event.msg_buf = malloc(event.buf_len, M_IXGBE, M_ZERO | M_NOWAIT);
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if (!event.msg_buf) {
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device_printf(sc->dev, "Can not allocate buffer for "
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"event message\n");
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return;
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}
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do {
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error = ixgbe_aci_get_event(hw, &event, &pending);
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if (error) {
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device_printf(sc->dev, "Error getting event from "
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"FW:%d\n", error);
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break;
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}
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switch (le16toh(event.desc.opcode)) {
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case ixgbe_aci_opc_get_link_status:
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sc->task_requests |= IXGBE_REQUEST_TASK_LSC;
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break;
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case ixgbe_aci_opc_temp_tca_event:
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if (hw->adapter_stopped == FALSE)
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ixgbe_if_stop(ctx);
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device_printf(sc->dev,
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"CRITICAL: OVER TEMP!! PHY IS SHUT DOWN!!\n");
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device_printf(sc->dev, "System shutdown required!\n");
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break;
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default:
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device_printf(sc->dev,
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"Unknown FW event captured, opcode=0x%04X\n",
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le16toh(event.desc.opcode));
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break;
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}
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} while (pending);
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free(event.msg_buf, M_IXGBE);
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} /* ixgbe_handle_fw_event */
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/************************************************************************
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* ixgbe_if_stop - Stop the hardware
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*
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|
|
@ -3933,6 +4102,8 @@ ixgbe_if_update_admin_status(if_ctx_t ctx)
|
|||
}
|
||||
|
||||
/* Handle task requests from msix_link() */
|
||||
if (sc->task_requests & IXGBE_REQUEST_TASK_FWEVENT)
|
||||
ixgbe_handle_fw_event(ctx);
|
||||
if (sc->task_requests & IXGBE_REQUEST_TASK_MOD)
|
||||
ixgbe_handle_mod(ctx);
|
||||
if (sc->task_requests & IXGBE_REQUEST_TASK_MSF)
|
||||
|
|
@ -4020,6 +4191,9 @@ ixgbe_if_enable_intr(if_ctx_t ctx)
|
|||
mask |= IXGBE_EICR_GPI_SDP0_X540;
|
||||
mask |= IXGBE_EIMS_ECC;
|
||||
break;
|
||||
case ixgbe_mac_E610:
|
||||
mask |= IXGBE_EIMS_FW_EVENT;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
@ -4042,6 +4216,7 @@ ixgbe_if_enable_intr(if_ctx_t ctx)
|
|||
/* Don't autoclear Link */
|
||||
mask &= ~IXGBE_EIMS_OTHER;
|
||||
mask &= ~IXGBE_EIMS_LSC;
|
||||
mask &= ~IXGBE_EIMS_FW_EVENT;
|
||||
if (sc->feat_cap & IXGBE_FEATURE_SRIOV)
|
||||
mask &= ~IXGBE_EIMS_MAILBOX;
|
||||
IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
|
||||
|
|
@ -4060,7 +4235,7 @@ ixgbe_if_enable_intr(if_ctx_t ctx)
|
|||
} /* ixgbe_if_enable_intr */
|
||||
|
||||
/************************************************************************
|
||||
* ixgbe_disable_intr
|
||||
* ixgbe_if_disable_intr
|
||||
************************************************************************/
|
||||
static void
|
||||
ixgbe_if_disable_intr(if_ctx_t ctx)
|
||||
|
|
@ -4210,8 +4385,9 @@ ixgbe_intr(void *arg)
|
|||
|
||||
/* External PHY interrupt */
|
||||
if ((hw->phy.type == ixgbe_phy_x550em_ext_t) &&
|
||||
(eicr & IXGBE_EICR_GPI_SDP0_X540))
|
||||
(eicr & IXGBE_EICR_GPI_SDP0_X540)) {
|
||||
sc->task_requests |= IXGBE_REQUEST_TASK_PHY;
|
||||
}
|
||||
|
||||
return (FILTER_SCHEDULE_THREAD);
|
||||
} /* ixgbe_intr */
|
||||
|
|
@ -4253,7 +4429,7 @@ ixgbe_sysctl_flowcntl(SYSCTL_HANDLER_ARGS)
|
|||
int error, fc;
|
||||
|
||||
sc = (struct ixgbe_softc *)arg1;
|
||||
fc = sc->hw.fc.current_mode;
|
||||
fc = sc->hw.fc.requested_mode;
|
||||
|
||||
error = sysctl_handle_int(oidp, &fc, 0, req);
|
||||
if ((error) || (req->newptr == NULL))
|
||||
|
|
@ -4282,12 +4458,10 @@ ixgbe_set_flowcntl(struct ixgbe_softc *sc, int fc)
|
|||
case ixgbe_fc_rx_pause:
|
||||
case ixgbe_fc_tx_pause:
|
||||
case ixgbe_fc_full:
|
||||
sc->hw.fc.requested_mode = fc;
|
||||
if (sc->num_rx_queues > 1)
|
||||
ixgbe_disable_rx_drop(sc);
|
||||
break;
|
||||
case ixgbe_fc_none:
|
||||
sc->hw.fc.requested_mode = ixgbe_fc_none;
|
||||
if (sc->num_rx_queues > 1)
|
||||
ixgbe_enable_rx_drop(sc);
|
||||
break;
|
||||
|
|
@ -4295,6 +4469,8 @@ ixgbe_set_flowcntl(struct ixgbe_softc *sc, int fc)
|
|||
return (EINVAL);
|
||||
}
|
||||
|
||||
sc->hw.fc.requested_mode = fc;
|
||||
|
||||
/* Don't autoneg if forcing a value */
|
||||
sc->hw.fc.disable_fc_autoneg = true;
|
||||
ixgbe_fc_enable(&sc->hw);
|
||||
|
|
@ -5012,6 +5188,9 @@ ixgbe_init_device_features(struct ixgbe_softc *sc)
|
|||
if (sc->hw.device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP)
|
||||
sc->feat_cap &= ~IXGBE_FEATURE_LEGACY_IRQ;
|
||||
break;
|
||||
case ixgbe_mac_E610:
|
||||
sc->feat_cap |= IXGBE_FEATURE_RECOVERY_MODE;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -68,6 +68,8 @@ static const pci_vendor_info_t ixv_vendor_info_array[] =
|
|||
"Intel(R) X552 Virtual Function"),
|
||||
PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF,
|
||||
"Intel(R) X553 Virtual Function"),
|
||||
PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_VF,
|
||||
"Intel(R) E610 Virtual Function"),
|
||||
/* required last entry */
|
||||
PVID_END
|
||||
};
|
||||
|
|
@ -1020,6 +1022,9 @@ ixv_identify_hardware(if_ctx_t ctx)
|
|||
case IXGBE_DEV_ID_X550EM_A_VF:
|
||||
hw->mac.type = ixgbe_mac_X550EM_a_vf;
|
||||
break;
|
||||
case IXGBE_DEV_ID_E610_VF:
|
||||
hw->mac.type = ixgbe_mac_E610_vf;
|
||||
break;
|
||||
default:
|
||||
device_printf(dev, "unknown mac type\n");
|
||||
hw->mac.type = ixgbe_mac_unknown;
|
||||
|
|
@ -1955,6 +1960,7 @@ ixv_init_device_features(struct ixgbe_softc *sc)
|
|||
case ixgbe_mac_X550_vf:
|
||||
case ixgbe_mac_X550EM_x_vf:
|
||||
case ixgbe_mac_X550EM_a_vf:
|
||||
case ixgbe_mac_E610_vf:
|
||||
sc->feat_cap |= IXGBE_FEATURE_NEEDS_CTXD;
|
||||
sc->feat_cap |= IXGBE_FEATURE_RSS;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -86,6 +86,7 @@
|
|||
#include "ixgbe_phy.h"
|
||||
#include "ixgbe_vf.h"
|
||||
#include "ixgbe_features.h"
|
||||
#include "ixgbe_e610.h"
|
||||
|
||||
/* Tunables */
|
||||
|
||||
|
|
@ -195,6 +196,15 @@
|
|||
CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
|
||||
CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
|
||||
|
||||
/* All BASE-T Physical layers */
|
||||
#define IXGBE_PHYSICAL_LAYERS_BASE_T_ALL \
|
||||
(IXGBE_PHYSICAL_LAYER_10GBASE_T |\
|
||||
IXGBE_PHYSICAL_LAYER_5000BASE_T |\
|
||||
IXGBE_PHYSICAL_LAYER_2500BASE_T |\
|
||||
IXGBE_PHYSICAL_LAYER_1000BASE_T |\
|
||||
IXGBE_PHYSICAL_LAYER_100BASE_TX |\
|
||||
IXGBE_PHYSICAL_LAYER_10BASE_T)
|
||||
|
||||
#define IXGBE_CAPS (IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 | IFCAP_TSO | \
|
||||
IFCAP_LRO | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | \
|
||||
IFCAP_VLAN_HWCSUM | IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU | \
|
||||
|
|
@ -464,6 +474,7 @@ struct ixgbe_softc {
|
|||
/* Feature capable/enabled flags. See ixgbe_features.h */
|
||||
u32 feat_cap;
|
||||
u32 feat_en;
|
||||
u16 lse_mask;
|
||||
};
|
||||
|
||||
/* Precision Time Sync (IEEE 1588) defines */
|
||||
|
|
|
|||
|
|
@ -112,11 +112,15 @@ s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
|
|||
case ixgbe_mac_X550EM_a:
|
||||
status = ixgbe_init_ops_X550EM_a(hw);
|
||||
break;
|
||||
case ixgbe_mac_E610:
|
||||
status = ixgbe_init_ops_E610(hw);
|
||||
break;
|
||||
case ixgbe_mac_82599_vf:
|
||||
case ixgbe_mac_X540_vf:
|
||||
case ixgbe_mac_X550_vf:
|
||||
case ixgbe_mac_X550EM_x_vf:
|
||||
case ixgbe_mac_X550EM_a_vf:
|
||||
case ixgbe_mac_E610_vf:
|
||||
status = ixgbe_init_ops_vf(hw);
|
||||
break;
|
||||
default:
|
||||
|
|
@ -240,6 +244,18 @@ s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
|
|||
hw->mac.type = ixgbe_mac_X550EM_a_vf;
|
||||
hw->mvals = ixgbe_mvals_X550EM_a;
|
||||
break;
|
||||
case IXGBE_DEV_ID_E610_BACKPLANE:
|
||||
case IXGBE_DEV_ID_E610_SFP:
|
||||
case IXGBE_DEV_ID_E610_10G_T:
|
||||
case IXGBE_DEV_ID_E610_2_5G_T:
|
||||
case IXGBE_DEV_ID_E610_SGMII:
|
||||
hw->mac.type = ixgbe_mac_E610;
|
||||
hw->mvals = ixgbe_mvals_X550EM_a;
|
||||
break;
|
||||
case IXGBE_DEV_ID_E610_VF:
|
||||
hw->mac.type = ixgbe_mac_E610_vf;
|
||||
hw->mvals = ixgbe_mvals_X550EM_a;
|
||||
break;
|
||||
default:
|
||||
ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
|
||||
ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
|
||||
|
|
|
|||
|
|
@ -48,6 +48,7 @@ extern s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw);
|
|||
extern s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw);
|
||||
extern s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw);
|
||||
extern s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw);
|
||||
extern s32 ixgbe_init_ops_E610(struct ixgbe_hw *hw);
|
||||
extern s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw);
|
||||
|
||||
s32 ixgbe_set_mac_type(struct ixgbe_hw *hw);
|
||||
|
|
|
|||
|
|
@ -178,6 +178,7 @@ bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
|
|||
case IXGBE_DEV_ID_X550EM_A_SFP_N:
|
||||
case IXGBE_DEV_ID_X550EM_A_QSFP:
|
||||
case IXGBE_DEV_ID_X550EM_A_QSFP_N:
|
||||
case IXGBE_DEV_ID_E610_SFP:
|
||||
supported = false;
|
||||
break;
|
||||
default:
|
||||
|
|
@ -210,6 +211,8 @@ bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
|
|||
case IXGBE_DEV_ID_X550EM_A_10G_T:
|
||||
case IXGBE_DEV_ID_X550EM_A_1G_T:
|
||||
case IXGBE_DEV_ID_X550EM_A_1G_T_L:
|
||||
case IXGBE_DEV_ID_E610_10G_T:
|
||||
case IXGBE_DEV_ID_E610_2_5G_T:
|
||||
supported = true;
|
||||
break;
|
||||
default:
|
||||
|
|
@ -616,7 +619,8 @@ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
|
|||
}
|
||||
}
|
||||
|
||||
if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
|
||||
if (hw->mac.type == ixgbe_mac_X540 ||
|
||||
hw->mac.type == ixgbe_mac_X550) {
|
||||
if (hw->phy.id == 0)
|
||||
ixgbe_identify_phy(hw);
|
||||
hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
|
||||
|
|
@ -1037,6 +1041,9 @@ void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
|
|||
case IXGBE_PCI_LINK_SPEED_8000:
|
||||
hw->bus.speed = ixgbe_bus_speed_8000;
|
||||
break;
|
||||
case IXGBE_PCI_LINK_SPEED_16000:
|
||||
hw->bus.speed = ixgbe_bus_speed_16000;
|
||||
break;
|
||||
default:
|
||||
hw->bus.speed = ixgbe_bus_speed_unknown;
|
||||
break;
|
||||
|
|
@ -1059,7 +1066,9 @@ s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
|
|||
DEBUGFUNC("ixgbe_get_bus_info_generic");
|
||||
|
||||
/* Get the negotiated link width and speed from PCI config space */
|
||||
link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
|
||||
link_status = IXGBE_READ_PCIE_WORD(hw, hw->mac.type == ixgbe_mac_E610 ?
|
||||
IXGBE_PCI_LINK_STATUS_E610 :
|
||||
IXGBE_PCI_LINK_STATUS);
|
||||
|
||||
ixgbe_set_pci_config_data_generic(hw, link_status);
|
||||
|
||||
|
|
@ -1878,7 +1887,6 @@ static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
|
|||
|
||||
DEBUGFUNC("ixgbe_get_eeprom_semaphore");
|
||||
|
||||
|
||||
/* Get SMBI software semaphore between device drivers first */
|
||||
for (i = 0; i < timeout; i++) {
|
||||
/*
|
||||
|
|
@ -3363,7 +3371,6 @@ s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
|
|||
|
||||
DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
|
||||
|
||||
|
||||
secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
|
||||
secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
|
||||
IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
|
||||
|
|
@ -3692,6 +3699,10 @@ u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
|
|||
pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
|
||||
max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
|
||||
break;
|
||||
case ixgbe_mac_E610:
|
||||
pcie_offset = IXGBE_PCIE_MSIX_E610_CAPS;
|
||||
max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
|
||||
break;
|
||||
default:
|
||||
return msix_count;
|
||||
}
|
||||
|
|
@ -4139,7 +4150,6 @@ s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
|
|||
return IXGBE_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* ixgbe_toggle_txdctl_generic - Toggle VF's queues
|
||||
* @hw: pointer to hardware structure
|
||||
|
|
@ -4323,7 +4333,8 @@ s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
|
|||
break;
|
||||
case IXGBE_LINKS_SPEED_100_82599:
|
||||
*speed = IXGBE_LINK_SPEED_100_FULL;
|
||||
if (hw->mac.type == ixgbe_mac_X550) {
|
||||
if (hw->mac.type == ixgbe_mac_X550 ||
|
||||
hw->mac.type == ixgbe_mac_E610) {
|
||||
if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
|
||||
*speed = IXGBE_LINK_SPEED_5GB_FULL;
|
||||
}
|
||||
|
|
@ -5494,6 +5505,7 @@ void ixgbe_get_nvm_version(struct ixgbe_hw *hw,
|
|||
case ixgbe_mac_X550:
|
||||
case ixgbe_mac_X550EM_x:
|
||||
case ixgbe_mac_X550EM_a:
|
||||
case ixgbe_mac_E610:
|
||||
/* version of eeprom section */
|
||||
if (ixgbe_read_eeprom(hw, NVM_EEP_OFFSET_X540, &word))
|
||||
word = NVM_VER_INVALID;
|
||||
|
|
@ -5512,6 +5524,7 @@ void ixgbe_get_nvm_version(struct ixgbe_hw *hw,
|
|||
case ixgbe_mac_X550:
|
||||
case ixgbe_mac_X550EM_x:
|
||||
case ixgbe_mac_X550EM_a:
|
||||
case ixgbe_mac_E610:
|
||||
/* intel phy firmware version */
|
||||
if (ixgbe_read_eeprom(hw, NVM_EEP_PHY_OFF_X540, &word))
|
||||
word = NVM_VER_INVALID;
|
||||
|
|
|
|||
5567
sys/dev/ixgbe/ixgbe_e610.c
Normal file
5567
sys/dev/ixgbe/ixgbe_e610.c
Normal file
File diff suppressed because it is too large
Load diff
224
sys/dev/ixgbe/ixgbe_e610.h
Normal file
224
sys/dev/ixgbe/ixgbe_e610.h
Normal file
|
|
@ -0,0 +1,224 @@
|
|||
/******************************************************************************
|
||||
SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
Copyright (c) 2025, Intel Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Intel Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _IXGBE_E610_H_
|
||||
#define _IXGBE_E610_H_
|
||||
|
||||
#include "ixgbe_type.h"
|
||||
|
||||
void ixgbe_init_aci(struct ixgbe_hw *hw);
|
||||
void ixgbe_shutdown_aci(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_aci_send_cmd(struct ixgbe_hw *hw, struct ixgbe_aci_desc *desc,
|
||||
void *buf, u16 buf_size);
|
||||
bool ixgbe_aci_check_event_pending(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_aci_get_event(struct ixgbe_hw *hw, struct ixgbe_aci_event *e,
|
||||
bool *pending);
|
||||
|
||||
void ixgbe_fill_dflt_direct_cmd_desc(struct ixgbe_aci_desc *desc, u16 opcode);
|
||||
|
||||
s32 ixgbe_aci_get_fw_ver(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_aci_send_driver_ver(struct ixgbe_hw *hw, struct ixgbe_driver_ver *dv);
|
||||
s32 ixgbe_aci_set_pf_context(struct ixgbe_hw *hw, u8 pf_id);
|
||||
|
||||
s32 ixgbe_acquire_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res,
|
||||
enum ixgbe_aci_res_access_type access, u32 timeout);
|
||||
void ixgbe_release_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res);
|
||||
s32 ixgbe_aci_list_caps(struct ixgbe_hw *hw, void *buf, u16 buf_size,
|
||||
u32 *cap_count, enum ixgbe_aci_opc opc);
|
||||
s32 ixgbe_discover_dev_caps(struct ixgbe_hw *hw,
|
||||
struct ixgbe_hw_dev_caps *dev_caps);
|
||||
s32 ixgbe_discover_func_caps(struct ixgbe_hw* hw,
|
||||
struct ixgbe_hw_func_caps* func_caps);
|
||||
s32 ixgbe_get_caps(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_aci_disable_rxen(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_aci_get_phy_caps(struct ixgbe_hw *hw, bool qual_mods, u8 report_mode,
|
||||
struct ixgbe_aci_cmd_get_phy_caps_data *pcaps);
|
||||
bool ixgbe_phy_caps_equals_cfg(struct ixgbe_aci_cmd_get_phy_caps_data *caps,
|
||||
struct ixgbe_aci_cmd_set_phy_cfg_data *cfg);
|
||||
void ixgbe_copy_phy_caps_to_cfg(struct ixgbe_aci_cmd_get_phy_caps_data *caps,
|
||||
struct ixgbe_aci_cmd_set_phy_cfg_data *cfg);
|
||||
s32 ixgbe_aci_set_phy_cfg(struct ixgbe_hw *hw,
|
||||
struct ixgbe_aci_cmd_set_phy_cfg_data *cfg);
|
||||
s32 ixgbe_aci_set_link_restart_an(struct ixgbe_hw *hw, bool ena_link);
|
||||
s32 ixgbe_update_link_info(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_get_link_status(struct ixgbe_hw *hw, bool *link_up);
|
||||
s32 ixgbe_aci_get_link_info(struct ixgbe_hw *hw, bool ena_lse,
|
||||
struct ixgbe_link_status *link);
|
||||
s32 ixgbe_aci_set_event_mask(struct ixgbe_hw *hw, u8 port_num, u16 mask);
|
||||
s32 ixgbe_configure_lse(struct ixgbe_hw *hw, bool activate, u16 mask);
|
||||
|
||||
s32 ixgbe_aci_get_netlist_node(struct ixgbe_hw *hw,
|
||||
struct ixgbe_aci_cmd_get_link_topo *cmd,
|
||||
u8 *node_part_number, u16 *node_handle);
|
||||
s32 ixgbe_find_netlist_node(struct ixgbe_hw *hw, u8 node_type_ctx,
|
||||
u8 node_part_number, u16 *node_handle);
|
||||
s32 ixgbe_aci_read_i2c(struct ixgbe_hw *hw,
|
||||
struct ixgbe_aci_cmd_link_topo_addr topo_addr,
|
||||
u16 bus_addr, __le16 addr, u8 params, u8 *data);
|
||||
s32 ixgbe_aci_write_i2c(struct ixgbe_hw *hw,
|
||||
struct ixgbe_aci_cmd_link_topo_addr topo_addr,
|
||||
u16 bus_addr, __le16 addr, u8 params, u8 *data);
|
||||
|
||||
s32 ixgbe_aci_set_port_id_led(struct ixgbe_hw *hw, bool orig_mode);
|
||||
s32 ixgbe_aci_set_gpio(struct ixgbe_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
|
||||
bool value);
|
||||
s32 ixgbe_aci_get_gpio(struct ixgbe_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
|
||||
bool *value);
|
||||
s32 ixgbe_aci_sff_eeprom(struct ixgbe_hw *hw, u16 lport, u8 bus_addr,
|
||||
u16 mem_addr, u8 page, u8 page_bank_ctrl, u8 *data,
|
||||
u8 length, bool write);
|
||||
s32 ixgbe_aci_prog_topo_dev_nvm(struct ixgbe_hw *hw,
|
||||
struct ixgbe_aci_cmd_link_topo_params *topo_params);
|
||||
s32 ixgbe_aci_read_topo_dev_nvm(struct ixgbe_hw *hw,
|
||||
struct ixgbe_aci_cmd_link_topo_params *topo_params,
|
||||
u32 start_address, u8 *data, u8 data_size);
|
||||
|
||||
s32 ixgbe_acquire_nvm(struct ixgbe_hw *hw,
|
||||
enum ixgbe_aci_res_access_type access);
|
||||
void ixgbe_release_nvm(struct ixgbe_hw *hw);
|
||||
|
||||
s32 ixgbe_aci_read_nvm(struct ixgbe_hw *hw, u16 module_typeid, u32 offset,
|
||||
u16 length, void *data, bool last_command,
|
||||
bool read_shadow_ram);
|
||||
|
||||
s32 ixgbe_aci_erase_nvm(struct ixgbe_hw *hw, u16 module_typeid);
|
||||
s32 ixgbe_aci_update_nvm(struct ixgbe_hw *hw, u16 module_typeid,
|
||||
u32 offset, u16 length, void *data,
|
||||
bool last_command, u8 command_flags);
|
||||
|
||||
s32 ixgbe_aci_read_nvm_cfg(struct ixgbe_hw *hw, u8 cmd_flags,
|
||||
u16 field_id, void *data, u16 buf_size,
|
||||
u16 *elem_count);
|
||||
s32 ixgbe_aci_write_nvm_cfg(struct ixgbe_hw *hw, u8 cmd_flags,
|
||||
void *data, u16 buf_size, u16 elem_count);
|
||||
|
||||
s32 ixgbe_nvm_validate_checksum(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_nvm_recalculate_checksum(struct ixgbe_hw *hw);
|
||||
|
||||
s32 ixgbe_nvm_write_activate(struct ixgbe_hw *hw, u16 cmd_flags,
|
||||
u8 *response_flags);
|
||||
|
||||
s32 ixgbe_get_nvm_minsrevs(struct ixgbe_hw *hw, struct ixgbe_minsrev_info *minsrevs);
|
||||
s32 ixgbe_update_nvm_minsrevs(struct ixgbe_hw *hw, struct ixgbe_minsrev_info *minsrevs);
|
||||
|
||||
s32 ixgbe_get_inactive_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm);
|
||||
s32 ixgbe_get_active_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm);
|
||||
|
||||
s32 ixgbe_get_inactive_netlist_ver(struct ixgbe_hw *hw, struct ixgbe_netlist_info *netlist);
|
||||
s32 ixgbe_init_nvm(struct ixgbe_hw *hw);
|
||||
|
||||
s32 ixgbe_sanitize_operate(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_sanitize_nvm(struct ixgbe_hw *hw, u8 cmd_flags, u8 *values);
|
||||
|
||||
s32 ixgbe_read_sr_word_aci(struct ixgbe_hw *hw, u16 offset, u16 *data);
|
||||
s32 ixgbe_read_sr_buf_aci(struct ixgbe_hw *hw, u16 offset, u16 *words, u16 *data);
|
||||
s32 ixgbe_read_flat_nvm(struct ixgbe_hw *hw, u32 offset, u32 *length,
|
||||
u8 *data, bool read_shadow_ram);
|
||||
|
||||
s32 ixgbe_write_sr_word_aci(struct ixgbe_hw *hw, u32 offset, const u16 *data);
|
||||
s32 ixgbe_write_sr_buf_aci(struct ixgbe_hw *hw, u32 offset, u16 words, const u16 *data);
|
||||
|
||||
s32 ixgbe_aci_alternate_write(struct ixgbe_hw *hw, u32 reg_addr0,
|
||||
u32 reg_val0, u32 reg_addr1, u32 reg_val1);
|
||||
s32 ixgbe_aci_alternate_read(struct ixgbe_hw *hw, u32 reg_addr0,
|
||||
u32 *reg_val0, u32 reg_addr1, u32 *reg_val1);
|
||||
s32 ixgbe_aci_alternate_write_done(struct ixgbe_hw *hw, u8 bios_mode,
|
||||
bool *reset_needed);
|
||||
s32 ixgbe_aci_alternate_clear(struct ixgbe_hw *hw);
|
||||
|
||||
s32 ixgbe_aci_get_internal_data(struct ixgbe_hw *hw, u16 cluster_id,
|
||||
u16 table_id, u32 start, void *buf,
|
||||
u16 buf_size, u16 *ret_buf_size,
|
||||
u16 *ret_next_cluster, u16 *ret_next_table,
|
||||
u32 *ret_next_index);
|
||||
|
||||
s32 ixgbe_handle_nvm_access(struct ixgbe_hw *hw,
|
||||
struct ixgbe_nvm_access_cmd *cmd,
|
||||
struct ixgbe_nvm_access_data *data);
|
||||
|
||||
s32 ixgbe_aci_set_health_status_config(struct ixgbe_hw *hw, u8 event_source);
|
||||
|
||||
/* E610 operations */
|
||||
s32 ixgbe_init_ops_E610(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_reset_hw_E610(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_start_hw_E610(struct ixgbe_hw *hw);
|
||||
enum ixgbe_media_type ixgbe_get_media_type_E610(struct ixgbe_hw *hw);
|
||||
u64 ixgbe_get_supported_physical_layer_E610(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_setup_link_E610(struct ixgbe_hw *hw, ixgbe_link_speed speed,
|
||||
bool autoneg_wait);
|
||||
s32 ixgbe_check_link_E610(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
|
||||
bool *link_up, bool link_up_wait_to_complete);
|
||||
s32 ixgbe_get_link_capabilities_E610(struct ixgbe_hw *hw,
|
||||
ixgbe_link_speed *speed,
|
||||
bool *autoneg);
|
||||
s32 ixgbe_cfg_phy_fc(struct ixgbe_hw *hw,
|
||||
struct ixgbe_aci_cmd_set_phy_cfg_data *cfg,
|
||||
enum ixgbe_fc_mode req_mode);
|
||||
s32 ixgbe_setup_fc_E610(struct ixgbe_hw *hw);
|
||||
void ixgbe_fc_autoneg_E610(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_set_fw_drv_ver_E610(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
|
||||
u8 sub, u16 len, const char *driver_ver);
|
||||
void ixgbe_disable_rx_E610(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_setup_eee_E610(struct ixgbe_hw *hw, bool enable_eee);
|
||||
bool ixgbe_fw_recovery_mode_E610(struct ixgbe_hw *hw);
|
||||
bool ixgbe_fw_rollback_mode_E610(struct ixgbe_hw *hw);
|
||||
bool ixgbe_get_fw_tsam_mode_E610(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_init_phy_ops_E610(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_identify_phy_E610(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_identify_module_E610(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_setup_phy_link_E610(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_get_phy_firmware_version_E610(struct ixgbe_hw *hw,
|
||||
u16 *firmware_version);
|
||||
s32 ixgbe_read_i2c_sff8472_E610(struct ixgbe_hw *hw, u8 byte_offset,
|
||||
u8 *sff8472_data);
|
||||
s32 ixgbe_read_i2c_eeprom_E610(struct ixgbe_hw *hw, u8 byte_offset,
|
||||
u8 *eeprom_data);
|
||||
s32 ixgbe_write_i2c_eeprom_E610(struct ixgbe_hw *hw, u8 byte_offset,
|
||||
u8 eeprom_data);
|
||||
s32 ixgbe_check_overtemp_E610(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_set_phy_power_E610(struct ixgbe_hw *hw, bool on);
|
||||
s32 ixgbe_enter_lplu_E610(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_init_eeprom_params_E610(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_read_ee_aci_E610(struct ixgbe_hw *hw, u16 offset, u16 *data);
|
||||
s32 ixgbe_read_ee_aci_buffer_E610(struct ixgbe_hw *hw, u16 offset,
|
||||
u16 words, u16 *data);
|
||||
s32 ixgbe_write_ee_aci_E610(struct ixgbe_hw *hw, u16 offset, u16 data);
|
||||
s32 ixgbe_write_ee_aci_buffer_E610(struct ixgbe_hw *hw, u16 offset,
|
||||
u16 words, u16 *data);
|
||||
s32 ixgbe_calc_eeprom_checksum_E610(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_update_eeprom_checksum_E610(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_validate_eeprom_checksum_E610(struct ixgbe_hw *hw, u16 *checksum_val);
|
||||
s32 ixgbe_read_pba_string_E610(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size);
|
||||
|
||||
#endif /* _IXGBE_E610_H_ */
|
||||
|
|
@ -114,3 +114,29 @@ ixgbe_link_speed_to_baudrate(ixgbe_link_speed speed)
|
|||
|
||||
return baudrate;
|
||||
}
|
||||
|
||||
void
|
||||
ixgbe_init_lock(struct ixgbe_lock *lock)
|
||||
{
|
||||
mtx_init(&lock->mutex, "mutex",
|
||||
"ixgbe ACI lock", MTX_DEF | MTX_DUPOK);
|
||||
}
|
||||
|
||||
void
|
||||
ixgbe_acquire_lock(struct ixgbe_lock *lock)
|
||||
{
|
||||
mtx_lock(&lock->mutex);
|
||||
}
|
||||
|
||||
void
|
||||
ixgbe_release_lock(struct ixgbe_lock *lock)
|
||||
{
|
||||
mtx_unlock(&lock->mutex);
|
||||
}
|
||||
|
||||
void
|
||||
ixgbe_destroy_lock(struct ixgbe_lock *lock)
|
||||
{
|
||||
if (mtx_initialized(&lock->mutex))
|
||||
mtx_destroy(&lock->mutex);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -133,7 +133,9 @@ enum {
|
|||
/* XXX these need to be revisited */
|
||||
#define IXGBE_CPU_TO_LE16 htole16
|
||||
#define IXGBE_CPU_TO_LE32 htole32
|
||||
#define IXGBE_LE16_TO_CPU le16toh
|
||||
#define IXGBE_LE32_TO_CPU le32toh
|
||||
#define IXGBE_LE64_TO_CPU le64toh
|
||||
#define IXGBE_LE32_TO_CPUS(x) *(x) = le32dec(x)
|
||||
#define IXGBE_CPU_TO_BE16 htobe16
|
||||
#define IXGBE_CPU_TO_BE32 htobe32
|
||||
|
|
@ -146,6 +148,7 @@ typedef int16_t s16;
|
|||
typedef uint32_t u32;
|
||||
typedef int32_t s32;
|
||||
typedef uint64_t u64;
|
||||
typedef int64_t s64;
|
||||
#ifndef __bool_true_false_are_defined
|
||||
typedef boolean_t bool;
|
||||
#endif
|
||||
|
|
@ -195,6 +198,11 @@ struct ixgbe_osdep
|
|||
bus_space_handle_t mem_bus_space_handle;
|
||||
};
|
||||
|
||||
struct ixgbe_lock
|
||||
{
|
||||
struct mtx mutex;
|
||||
};
|
||||
|
||||
/* These routines need struct ixgbe_hw declared */
|
||||
struct ixgbe_hw;
|
||||
device_t ixgbe_dev_from_hw(struct ixgbe_hw *hw);
|
||||
|
|
@ -222,4 +230,27 @@ extern void ixgbe_write_reg_array(struct ixgbe_hw *, u32, u32, u32);
|
|||
#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, val) \
|
||||
ixgbe_write_reg_array(a, reg, offset, val)
|
||||
|
||||
void ixgbe_init_lock(struct ixgbe_lock *);
|
||||
void ixgbe_destroy_lock(struct ixgbe_lock *);
|
||||
void ixgbe_acquire_lock(struct ixgbe_lock *);
|
||||
void ixgbe_release_lock(struct ixgbe_lock *);
|
||||
|
||||
static inline void *
|
||||
ixgbe_calloc(struct ixgbe_hw __unused *hw, size_t count, size_t size)
|
||||
{
|
||||
return (malloc(count * size, M_DEVBUF, M_ZERO | M_NOWAIT));
|
||||
}
|
||||
|
||||
static inline void *
|
||||
ixgbe_malloc(struct ixgbe_hw __unused *hw, size_t size)
|
||||
{
|
||||
return (malloc(size, M_DEVBUF, M_ZERO | M_NOWAIT));
|
||||
}
|
||||
|
||||
static inline void
|
||||
ixgbe_free(struct ixgbe_hw __unused *hw, void *addr)
|
||||
{
|
||||
free(addr, M_DEVBUF);
|
||||
}
|
||||
|
||||
#endif /* _IXGBE_OSDEP_H_ */
|
||||
|
|
|
|||
|
|
@ -74,6 +74,7 @@
|
|||
*/
|
||||
|
||||
#include "ixgbe_osdep.h"
|
||||
#include "ixgbe_type_e610.h"
|
||||
|
||||
/* Override this by setting IOMEM in your ixgbe_osdep.h header */
|
||||
#define IOMEM
|
||||
|
|
@ -150,12 +151,19 @@
|
|||
#define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD
|
||||
#define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE
|
||||
#define IXGBE_DEV_ID_X550EM_X_XFI 0x15B0
|
||||
#define IXGBE_DEV_ID_E610_BACKPLANE 0x57AE
|
||||
#define IXGBE_DEV_ID_E610_SFP 0x57AF
|
||||
#define IXGBE_DEV_ID_E610_10G_T 0x57B0
|
||||
#define IXGBE_DEV_ID_E610_2_5G_T 0x57B1
|
||||
#define IXGBE_DEV_ID_E610_SGMII 0x57B2
|
||||
#define IXGBE_DEV_ID_X550_VF_HV 0x1564
|
||||
#define IXGBE_DEV_ID_X550_VF 0x1565
|
||||
#define IXGBE_DEV_ID_X550EM_A_VF 0x15C5
|
||||
#define IXGBE_DEV_ID_X550EM_A_VF_HV 0x15B4
|
||||
#define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
|
||||
#define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9
|
||||
#define IXGBE_DEV_ID_E610_VF 0x57AD
|
||||
#define IXGBE_SUBDEV_ID_E610_VF_HV 0x0001
|
||||
|
||||
#define IXGBE_CAT(r, m) IXGBE_##r##m
|
||||
|
||||
|
|
@ -1969,6 +1977,7 @@ enum {
|
|||
#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
|
||||
#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
|
||||
#define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */
|
||||
#define IXGBE_EICR_FW_EVENT 0x00200000 /* Async FW event */
|
||||
#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
|
||||
#define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */
|
||||
#define IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */
|
||||
|
|
@ -2004,6 +2013,7 @@ enum {
|
|||
#define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */
|
||||
#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
|
||||
#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
|
||||
#define IXGBE_EICS_FW_EVENT IXGBE_EICR_FW_EVENT /* Async FW event */
|
||||
#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
|
||||
#define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
|
||||
#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
|
||||
|
|
@ -2025,6 +2035,7 @@ enum {
|
|||
#define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */
|
||||
#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
|
||||
#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
|
||||
#define IXGBE_EIMS_FW_EVENT IXGBE_EICR_FW_EVENT /* Async FW event */
|
||||
#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
|
||||
#define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermal Sensor Event */
|
||||
#define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
|
||||
|
|
@ -2047,6 +2058,7 @@ enum {
|
|||
#define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */
|
||||
#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
|
||||
#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
|
||||
#define IXGBE_EIMC_FW_EVENT IXGBE_EICR_FW_EVENT /* Async FW event */
|
||||
#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
|
||||
#define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
|
||||
#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
|
||||
|
|
@ -2454,6 +2466,7 @@ enum {
|
|||
#define IXGBE_82599_SERIAL_NUMBER_MAC_ADDR 0x11
|
||||
#define IXGBE_X550_SERIAL_NUMBER_MAC_ADDR 0x04
|
||||
|
||||
#define IXGBE_PCIE_MSIX_E610_CAPS 0xB2
|
||||
#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
|
||||
#define IXGBE_MAX_MSIX_VECTORS_82599 0x40
|
||||
#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
|
||||
|
|
@ -2571,6 +2584,7 @@ enum {
|
|||
#define IXGBE_PCI_DEVICE_STATUS 0xAA
|
||||
#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020
|
||||
#define IXGBE_PCI_LINK_STATUS 0xB2
|
||||
#define IXGBE_PCI_LINK_STATUS_E610 0x82
|
||||
#define IXGBE_PCI_DEVICE_CONTROL2 0xC8
|
||||
#define IXGBE_PCI_LINK_WIDTH 0x3F0
|
||||
#define IXGBE_PCI_LINK_WIDTH_1 0x10
|
||||
|
|
@ -2581,6 +2595,7 @@ enum {
|
|||
#define IXGBE_PCI_LINK_SPEED_2500 0x1
|
||||
#define IXGBE_PCI_LINK_SPEED_5000 0x2
|
||||
#define IXGBE_PCI_LINK_SPEED_8000 0x3
|
||||
#define IXGBE_PCI_LINK_SPEED_16000 0x4
|
||||
#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
|
||||
#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
|
||||
#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
|
||||
|
|
@ -3743,6 +3758,8 @@ enum ixgbe_mac_type {
|
|||
ixgbe_mac_X550_vf,
|
||||
ixgbe_mac_X550EM_x_vf,
|
||||
ixgbe_mac_X550EM_a_vf,
|
||||
ixgbe_mac_E610,
|
||||
ixgbe_mac_E610_vf,
|
||||
ixgbe_num_macs
|
||||
};
|
||||
|
||||
|
|
@ -3822,7 +3839,9 @@ enum ixgbe_media_type {
|
|||
ixgbe_media_type_copper,
|
||||
ixgbe_media_type_backplane,
|
||||
ixgbe_media_type_cx4,
|
||||
ixgbe_media_type_virtual
|
||||
ixgbe_media_type_virtual,
|
||||
ixgbe_media_type_da,
|
||||
ixgbe_media_type_aui
|
||||
};
|
||||
|
||||
/* Flow Control Settings */
|
||||
|
|
@ -3831,6 +3850,7 @@ enum ixgbe_fc_mode {
|
|||
ixgbe_fc_rx_pause,
|
||||
ixgbe_fc_tx_pause,
|
||||
ixgbe_fc_full,
|
||||
ixgbe_fc_auto,
|
||||
ixgbe_fc_default
|
||||
};
|
||||
|
||||
|
|
@ -3863,6 +3883,7 @@ enum ixgbe_bus_speed {
|
|||
ixgbe_bus_speed_2500 = 2500,
|
||||
ixgbe_bus_speed_5000 = 5000,
|
||||
ixgbe_bus_speed_8000 = 8000,
|
||||
ixgbe_bus_speed_16000 = 16000,
|
||||
ixgbe_bus_speed_reserved
|
||||
};
|
||||
|
||||
|
|
@ -4007,6 +4028,7 @@ struct ixgbe_eeprom_operations {
|
|||
s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
|
||||
s32 (*update_checksum)(struct ixgbe_hw *);
|
||||
s32 (*calc_checksum)(struct ixgbe_hw *);
|
||||
s32 (*read_pba_string)(struct ixgbe_hw *, u8 *, u32);
|
||||
};
|
||||
|
||||
struct ixgbe_mac_operations {
|
||||
|
|
@ -4118,6 +4140,10 @@ struct ixgbe_mac_operations {
|
|||
void (*mdd_event)(struct ixgbe_hw *hw, u32 *vf_bitmap);
|
||||
void (*restore_mdd_vf)(struct ixgbe_hw *hw, u32 vf);
|
||||
bool (*fw_recovery_mode)(struct ixgbe_hw *hw);
|
||||
bool (*fw_rollback_mode)(struct ixgbe_hw *hw);
|
||||
bool (*get_fw_tsam_mode)(struct ixgbe_hw *hw);
|
||||
s32 (*get_fw_version)(struct ixgbe_hw *hw);
|
||||
s32 (*get_nvm_version)(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm);
|
||||
};
|
||||
|
||||
struct ixgbe_phy_operations {
|
||||
|
|
@ -4162,6 +4188,9 @@ struct ixgbe_link_operations {
|
|||
struct ixgbe_link_info {
|
||||
struct ixgbe_link_operations ops;
|
||||
u8 addr;
|
||||
struct ixgbe_link_status link_info;
|
||||
struct ixgbe_link_status link_info_old;
|
||||
u8 get_link_info;
|
||||
};
|
||||
|
||||
struct ixgbe_eeprom_info {
|
||||
|
|
@ -4233,6 +4262,9 @@ struct ixgbe_phy_info {
|
|||
bool reset_if_overtemp;
|
||||
bool qsfp_shared_i2c_bus;
|
||||
u32 nw_mng_if_sel;
|
||||
u64 phy_type_low;
|
||||
u64 phy_type_high;
|
||||
struct ixgbe_aci_cmd_set_phy_cfg_data curr_user_phy_cfg;
|
||||
};
|
||||
|
||||
#include "ixgbe_mbx.h"
|
||||
|
|
@ -4263,6 +4295,22 @@ struct ixgbe_hw {
|
|||
/* XXX flag for workaround to prevent reading an sfp[+] slot with nothing connected to it. */
|
||||
bool sfp_probe_timed_out;
|
||||
u32 fw_rst_cnt;
|
||||
u8 api_branch;
|
||||
u8 api_maj_ver;
|
||||
u8 api_min_ver;
|
||||
u8 api_patch;
|
||||
u8 fw_branch;
|
||||
u8 fw_maj_ver;
|
||||
u8 fw_min_ver;
|
||||
u8 fw_patch;
|
||||
u32 fw_build;
|
||||
struct ixgbe_aci_info aci;
|
||||
struct ixgbe_flash_info flash;
|
||||
struct ixgbe_hw_dev_caps dev_caps;
|
||||
struct ixgbe_hw_func_caps func_caps;
|
||||
struct ixgbe_fwlog_cfg fwlog_cfg;
|
||||
bool fwlog_support_ena;
|
||||
struct ixgbe_fwlog_ring fwlog_ring;
|
||||
};
|
||||
|
||||
#define ixgbe_call_func(hw, func, params, error) \
|
||||
|
|
@ -4314,6 +4362,24 @@ struct ixgbe_hw {
|
|||
#define IXGBE_ERR_MBX_NOMSG -42
|
||||
#define IXGBE_ERR_TIMEOUT -43
|
||||
|
||||
#define IXGBE_ERR_NOT_SUPPORTED -45
|
||||
#define IXGBE_ERR_OUT_OF_RANGE -46
|
||||
|
||||
#define IXGBE_ERR_NVM -50
|
||||
#define IXGBE_ERR_NVM_CHECKSUM -51
|
||||
#define IXGBE_ERR_BUF_TOO_SHORT -52
|
||||
#define IXGBE_ERR_NVM_BLANK_MODE -53
|
||||
#define IXGBE_ERR_INVAL_SIZE -54
|
||||
#define IXGBE_ERR_DOES_NOT_EXIST -55
|
||||
|
||||
#define IXGBE_ERR_ACI_ERROR -100
|
||||
#define IXGBE_ERR_ACI_DISABLED -101
|
||||
#define IXGBE_ERR_ACI_TIMEOUT -102
|
||||
#define IXGBE_ERR_ACI_BUSY -103
|
||||
#define IXGBE_ERR_ACI_NO_WORK -104
|
||||
#define IXGBE_ERR_ACI_NO_EVENTS -105
|
||||
#define IXGBE_ERR_FW_API_VER -106
|
||||
|
||||
#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
|
||||
|
||||
|
||||
|
|
@ -4542,5 +4608,6 @@ struct ixgbe_bypass_eeprom {
|
|||
#define IXGBE_REQUEST_TASK_FDIR 0x08
|
||||
#define IXGBE_REQUEST_TASK_PHY 0x10
|
||||
#define IXGBE_REQUEST_TASK_LSC 0x20
|
||||
#define IXGBE_REQUEST_TASK_FWEVENT 0x40
|
||||
|
||||
#endif /* _IXGBE_TYPE_H_ */
|
||||
|
|
|
|||
2278
sys/dev/ixgbe/ixgbe_type_e610.h
Normal file
2278
sys/dev/ixgbe/ixgbe_type_e610.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -656,7 +656,8 @@ s32 ixgbe_check_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
|
|||
break;
|
||||
case IXGBE_LINKS_SPEED_100_82599:
|
||||
*speed = IXGBE_LINK_SPEED_100_FULL;
|
||||
if (hw->mac.type == ixgbe_mac_X550_vf) {
|
||||
if (hw->mac.type == ixgbe_mac_X550_vf ||
|
||||
hw->mac.type == ixgbe_mac_E610_vf) {
|
||||
if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
|
||||
*speed = IXGBE_LINK_SPEED_5GB_FULL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ SRCS += if_ix.c if_bypass.c if_fdir.c if_sriov.c ix_txrx.c ixgbe_osdep.c
|
|||
# Shared source
|
||||
SRCS += ixgbe_common.c ixgbe_api.c ixgbe_phy.c ixgbe_mbx.c ixgbe_vf.c
|
||||
SRCS += ixgbe_dcb.c ixgbe_dcb_82598.c ixgbe_dcb_82599.c
|
||||
SRCS += ixgbe_82598.c ixgbe_82599.c ixgbe_x540.c ixgbe_x550.c
|
||||
SRCS += ixgbe_82598.c ixgbe_82599.c ixgbe_x540.c ixgbe_x550.c ixgbe_e610.c
|
||||
CFLAGS+= -I${SRCTOP}/sys/dev/ixgbe
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ SRCS += if_ixv.c if_fdir.c ix_txrx.c ixgbe_osdep.c
|
|||
# Shared source
|
||||
SRCS += ixgbe_common.c ixgbe_api.c ixgbe_phy.c ixgbe_mbx.c ixgbe_vf.c
|
||||
SRCS += ixgbe_dcb.c ixgbe_dcb_82598.c ixgbe_dcb_82599.c
|
||||
SRCS += ixgbe_82598.c ixgbe_82599.c ixgbe_x540.c ixgbe_x550.c
|
||||
SRCS += ixgbe_82598.c ixgbe_82599.c ixgbe_x540.c ixgbe_x550.c ixgbe_e610.c
|
||||
CFLAGS+= -I${SRCTOP}/sys/dev/ixgbe
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
|
|
|
|||
Loading…
Reference in a new issue