If the L2 cache type is PIPT, pass a physical address for a flush.

While this is technically more correct, I don't think it much matters,
because the only thing in the tree that calls cpu_flush_dcache() is md(4)
and I'm > 99% sure it's bogus that it does so; md has no ability to do
anything that can perturb data cache coherency.

sys/arm/arm/machdep.c

@@ -410,7 +410,11 @@ cpu_flush_dcache(void *ptr, size_t len)
 {
 
 	cpu_dcache_wb_range((uintptr_t)ptr, len);
+#ifdef ARM_L2_PIPT
+	cpu_l2cache_wb_range((uintptr_t)vtophys(ptr), len);
+#else
 	cpu_l2cache_wb_range((uintptr_t)ptr, len);
+#endif
 }
 
 /* Get current clock frequency for the given cpu id. */