From b7c1fc50a42d407a553505f45dbdecb2955e7239 Mon Sep 17 00:00:00 2001 From: Ian Lepore Date: Sun, 23 Feb 2014 22:52:48 +0000 Subject: [PATCH] If the L2 cache type is PIPT, pass a physical address for a flush. While this is technically more correct, I don't think it much matters, because the only thing in the tree that calls cpu_flush_dcache() is md(4) and I'm > 99% sure it's bogus that it does so; md has no ability to do anything that can perturb data cache coherency. --- sys/arm/arm/machdep.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sys/arm/arm/machdep.c b/sys/arm/arm/machdep.c index 8544dc13502..1386210251f 100644 --- a/sys/arm/arm/machdep.c +++ b/sys/arm/arm/machdep.c @@ -410,7 +410,11 @@ cpu_flush_dcache(void *ptr, size_t len) { cpu_dcache_wb_range((uintptr_t)ptr, len); +#ifdef ARM_L2_PIPT + cpu_l2cache_wb_range((uintptr_t)vtophys(ptr), len); +#else cpu_l2cache_wb_range((uintptr_t)ptr, len); +#endif } /* Get current clock frequency for the given cpu id. */