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Remove fdt_pic_table code from MIPS, PowerPC, and x86, as it is no longer
used by anything. The equivalent functionality is provided by the PIC drivers themselves on PowerPC and this is a no-op on MIPS and x86.
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parent
f61b6fe561
commit
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3 changed files with 0 additions and 131 deletions
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@ -49,45 +49,3 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
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{ NULL, NULL }
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};
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/*
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* For PIC-free boards, provide a PIC decoder to be used with mips4k CP0
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* interrupt control directly.
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*/
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static int
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fdt_pic_decode_mips4k_cp0(phandle_t node, pcell_t *intr, int *interrupt,
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int *trig, int *pol)
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{
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if (!fdt_is_compatible(node, "mips,mips4k"))
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return (ENXIO);
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*interrupt = fdt32_to_cpu(intr[0]);
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*trig = INTR_TRIGGER_CONFORM;
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*pol = INTR_POLARITY_CONFORM;
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return (0);
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}
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/*
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* CHERI PIC decoder.
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*/
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static int
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fdt_pic_decode_beri(phandle_t node, pcell_t *intr, int *interrupt,
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int *trig, int *pol)
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{
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if (!fdt_is_compatible(node, "sri-cambridge,beri-pic"))
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return (ENXIO);
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*interrupt = fdt32_to_cpu(intr[0]);
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*trig = INTR_TRIGGER_CONFORM;
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*pol = INTR_POLARITY_CONFORM;
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return (0);
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}
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fdt_pic_decode_t fdt_pic_table[] = {
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&fdt_pic_decode_mips4k_cp0,
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&fdt_pic_decode_beri,
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NULL
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};
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@ -81,89 +81,3 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
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{ NULL, NULL }
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};
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static int
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fdt_pic_decode_iic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
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int *pol)
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{
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if (!fdt_is_compatible(node, "chrp,iic"))
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return (ENXIO);
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*interrupt = intr[0];
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switch (intr[1]) {
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case 0:
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/* Active L level */
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*trig = INTR_TRIGGER_LEVEL;
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*pol = INTR_POLARITY_LOW;
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break;
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case 1:
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/* Active H level */
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*trig = INTR_TRIGGER_LEVEL;
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*pol = INTR_POLARITY_HIGH;
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break;
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case 2:
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/* H to L edge */
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*trig = INTR_TRIGGER_EDGE;
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*pol = INTR_POLARITY_LOW;
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break;
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case 3:
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/* L to H edge */
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*trig = INTR_TRIGGER_EDGE;
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*pol = INTR_POLARITY_HIGH;
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break;
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default:
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*trig = INTR_TRIGGER_CONFORM;
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*pol = INTR_POLARITY_CONFORM;
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}
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return (0);
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}
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static int
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fdt_pic_decode_openpic(phandle_t node, pcell_t *intr, int *interrupt,
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int *trig, int *pol)
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{
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if (!fdt_is_compatible(node, "chrp,open-pic") &&
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!fdt_is_type(node, "open-pic"))
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return (ENXIO);
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/*
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* XXX The interrupt number read out from the MPC85XX device tree is
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* already offset by 16 to reflect the 'internal' IRQ range shift on
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* the OpenPIC.
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*/
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*interrupt = intr[0];
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switch (intr[1]) {
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case 0:
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/* L to H edge */
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*trig = INTR_TRIGGER_EDGE;
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*pol = INTR_POLARITY_HIGH;
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break;
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case 1:
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/* Active L level */
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*trig = INTR_TRIGGER_LEVEL;
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*pol = INTR_POLARITY_LOW;
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break;
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case 2:
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/* Active H level */
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*trig = INTR_TRIGGER_LEVEL;
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*pol = INTR_POLARITY_HIGH;
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break;
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case 3:
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/* H to L edge */
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*trig = INTR_TRIGGER_EDGE;
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*pol = INTR_POLARITY_LOW;
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break;
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default:
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*trig = INTR_TRIGGER_CONFORM;
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*pol = INTR_POLARITY_CONFORM;
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}
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return (0);
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}
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fdt_pic_decode_t fdt_pic_table[] = {
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&fdt_pic_decode_iic,
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&fdt_pic_decode_openpic,
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NULL
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};
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@ -46,6 +46,3 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
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{ NULL, NULL }
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};
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fdt_pic_decode_t fdt_pic_table[] = {
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NULL
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};
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