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Align virtual addressing entries.

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This is required due to C-compressed ISA extension option being turned on.

This fixes SMP operation in QEMU.

Sponsored by:	DARPA, AFRL
This commit is contained in:
Ruslan Bukin 2018-06-12 16:19:27 +00:00
parent 0c38b2d37c
commit a9063ba1d7
1 changed files with 4 additions and 0 deletions
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4
sys/riscv/riscv/locore.S
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@ -156,6 +156,8 @@ _start:
or s2, s2, t0
sfence.vma
csrw sptbr, s2
.align 2
va:
/* Setup supervisor trap vector */
@ -284,6 +286,8 @@ ENTRY(mpentry)
or s2, s2, t0
sfence.vma
csrw sptbr, s2
.align 2
mpva:
/* Setup supervisor trap vector */
la t0, cpu_exception_handler