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Set all of the "optimum performance" PHY registers for the 15D parts as

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well as the 15C since it seems to be required in practice.  The Linux
natsemi.c driver mostly does this as well.

PR:		kern/112179
Submitted by:	Mark Willson  mark - hydrus org uk
MFC after:	1 week
This commit is contained in:
John Baldwin 2008-07-30 17:28:49 +00:00
parent f5698581ca
commit a6c4b9deb4
1 changed files with 8 additions and 10 deletions
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18
sys/pci/if_sis.c
View file

@ -1898,20 +1898,18 @@ sis_initl(struct sis_softc *sc)
* Short Cable Receive Errors (MP21.E)
* also: Page 78 of the DP83815 data sheet (september 2002 version)
* recommends the following register settings "for optimum
* performance." for rev 15C. The driver from NS also sets
* the PHY_CR register for later versions.
* performance." for rev 15C. Set this also for 15D parts as
* they require it in practice.
*/
if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) {
CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
if (sc->sis_srr == NS_SRR_15C) {
/* set val for c2 */
CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
/* load/kill c2 */
CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
/* rais SD off, from 4 to c */
CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
}
/* set val for c2 */
CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
/* load/kill c2 */
CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
/* rais SD off, from 4 to c */
CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
}