From a6c4b9deb4655b2abd2ccfb31c5328a30e771cc1 Mon Sep 17 00:00:00 2001 From: John Baldwin Date: Wed, 30 Jul 2008 17:28:49 +0000 Subject: [PATCH] Set all of the "optimum performance" PHY registers for the 15D parts as well as the 15C since it seems to be required in practice. The Linux natsemi.c driver mostly does this as well. PR: kern/112179 Submitted by: Mark Willson mark - hydrus org uk MFC after: 1 week --- sys/pci/if_sis.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/sys/pci/if_sis.c b/sys/pci/if_sis.c index b22ff8d0232..f5fbe1ffd77 100644 --- a/sys/pci/if_sis.c +++ b/sys/pci/if_sis.c @@ -1898,20 +1898,18 @@ sis_initl(struct sis_softc *sc) * Short Cable Receive Errors (MP21.E) * also: Page 78 of the DP83815 data sheet (september 2002 version) * recommends the following register settings "for optimum - * performance." for rev 15C. The driver from NS also sets - * the PHY_CR register for later versions. + * performance." for rev 15C. Set this also for 15D parts as + * they require it in practice. */ if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) { CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); - if (sc->sis_srr == NS_SRR_15C) { - /* set val for c2 */ - CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); - /* load/kill c2 */ - CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); - /* rais SD off, from 4 to c */ - CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); - } + /* set val for c2 */ + CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); + /* load/kill c2 */ + CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); + /* rais SD off, from 4 to c */ + CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); CSR_WRITE_4(sc, NS_PHY_PAGE, 0); }