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arm64: Add TCR register masks

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These will be used by bhyve to implement page table walking.

Sponsored by:	Arm Ltd

(cherry picked from commit a35e47369f88e8c2e14b7371a1a5e1152680551f)
This commit is contained in:
Andrew Turner 2023-09-08 14:29:19 +01:00
parent 7a64b05196
commit 94f23ae15a
1 changed files with 4 additions and 1 deletions
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5
sys/arm64/include/armreg.h
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@ -2141,6 +2141,7 @@
#define TCR_IPS_44BIT (4UL << TCR_IPS_SHIFT)
#define TCR_IPS_48BIT (5UL << TCR_IPS_SHIFT)
#define TCR_TG1_SHIFT 30
#define TCR_TG1_MASK (3UL << TCR_TG1_SHIFT)
#define TCR_TG1_16K (1UL << TCR_TG1_SHIFT)
#define TCR_TG1_4K (2UL << TCR_TG1_SHIFT)
#define TCR_TG1_64K (3UL << TCR_TG1_SHIFT)
@ -2155,8 +2156,10 @@
#define TCR_A1_SHIFT 22
#define TCR_A1 (0x1UL << TCR_A1_SHIFT)
#define TCR_T1SZ_SHIFT 16
#define TCR_T1SZ_MASK (0x3fUL << TCR_T1SZ_SHIFT)
#define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT)
#define TCR_TG0_SHIFT 14
#define TCR_TG0_MASK (3UL << TCR_TG0_SHIFT)
#define TCR_TG0_4K (0UL << TCR_TG0_SHIFT)
#define TCR_TG0_64K (1UL << TCR_TG0_SHIFT)
#define TCR_TG0_16K (2UL << TCR_TG0_SHIFT)
@ -2170,7 +2173,7 @@
#define TCR_EPD0 (1UL << TCR_EPD0_SHIFT)
/* Bit 6 is reserved */
#define TCR_T0SZ_SHIFT 0
#define TCR_T0SZ_MASK 0x3f
#define TCR_T0SZ_MASK (0x3fUL << TCR_T0SZ_SHIFT)
#define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT)
#define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x))