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Add support for RISC-V ISA.

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Reviewed by:	andrew
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
Differential Revision:	https://reviews.freebsd.org/D5040
This commit is contained in:
Ruslan Bukin 2016-01-24 12:10:29 +00:00
parent 0a17d8c230
commit 7dd3aed9c9
2 changed files with 11 additions and 0 deletions
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3
lib/libproc/proc_bkpt.c
View file

@ -61,6 +61,9 @@ __FBSDID("$FreeBSD$");
#elif defined(__powerpc__)
#define BREAKPOINT_INSTR 0x7fe00008 /* trap */
#define BREAKPOINT_INSTR_SZ 4
#elif defined(__riscv__)
#define BREAKPOINT_INSTR 0x00100073 /* sbreak */
#define BREAKPOINT_INSTR_SZ 4
#else
#error "Add support for your architecture"
#endif

8
lib/libproc/proc_regs.c
View file

@ -66,6 +66,8 @@ proc_regget(struct proc_handle *phdl, proc_reg_t reg, unsigned long *regvalue)
*regvalue = regs.r_regs[PC];
#elif defined(__powerpc__)
*regvalue = regs.pc;
#elif defined(__riscv__)
*regvalue = regs.sepc;
#endif
break;
case REG_SP:
@ -81,6 +83,8 @@ proc_regget(struct proc_handle *phdl, proc_reg_t reg, unsigned long *regvalue)
*regvalue = regs.r_regs[SP];
#elif defined(__powerpc__)
*regvalue = regs.fixreg[1];
#elif defined(__riscv__)
*regvalue = regs.sp;
#endif
break;
default:
@ -117,6 +121,8 @@ proc_regset(struct proc_handle *phdl, proc_reg_t reg, unsigned long regvalue)
regs.r_regs[PC] = regvalue;
#elif defined(__powerpc__)
regs.pc = regvalue;
#elif defined(__riscv__)
regs.sepc = regvalue;
#endif
break;
case REG_SP:
@ -132,6 +138,8 @@ proc_regset(struct proc_handle *phdl, proc_reg_t reg, unsigned long regvalue)
regs.r_regs[PC] = regvalue;
#elif defined(__powerpc__)
regs.fixreg[1] = regvalue;
#elif defined(__riscv__)
regs.sp = regvalue;
#endif
break;
default: