From 7dd3aed9c9e4a50bd48d342ca1fa8222c73b4708 Mon Sep 17 00:00:00 2001 From: Ruslan Bukin Date: Sun, 24 Jan 2016 12:10:29 +0000 Subject: [PATCH] Add support for RISC-V ISA. Reviewed by: andrew Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D5040 --- lib/libproc/proc_bkpt.c | 3 +++ lib/libproc/proc_regs.c | 8 ++++++++ 2 files changed, 11 insertions(+) diff --git a/lib/libproc/proc_bkpt.c b/lib/libproc/proc_bkpt.c index f0ff5c5d770..4a100cbbd4e 100644 --- a/lib/libproc/proc_bkpt.c +++ b/lib/libproc/proc_bkpt.c @@ -61,6 +61,9 @@ __FBSDID("$FreeBSD$"); #elif defined(__powerpc__) #define BREAKPOINT_INSTR 0x7fe00008 /* trap */ #define BREAKPOINT_INSTR_SZ 4 +#elif defined(__riscv__) +#define BREAKPOINT_INSTR 0x00100073 /* sbreak */ +#define BREAKPOINT_INSTR_SZ 4 #else #error "Add support for your architecture" #endif diff --git a/lib/libproc/proc_regs.c b/lib/libproc/proc_regs.c index aae43ba1710..745fa099a92 100644 --- a/lib/libproc/proc_regs.c +++ b/lib/libproc/proc_regs.c @@ -66,6 +66,8 @@ proc_regget(struct proc_handle *phdl, proc_reg_t reg, unsigned long *regvalue) *regvalue = regs.r_regs[PC]; #elif defined(__powerpc__) *regvalue = regs.pc; +#elif defined(__riscv__) + *regvalue = regs.sepc; #endif break; case REG_SP: @@ -81,6 +83,8 @@ proc_regget(struct proc_handle *phdl, proc_reg_t reg, unsigned long *regvalue) *regvalue = regs.r_regs[SP]; #elif defined(__powerpc__) *regvalue = regs.fixreg[1]; +#elif defined(__riscv__) + *regvalue = regs.sp; #endif break; default: @@ -117,6 +121,8 @@ proc_regset(struct proc_handle *phdl, proc_reg_t reg, unsigned long regvalue) regs.r_regs[PC] = regvalue; #elif defined(__powerpc__) regs.pc = regvalue; +#elif defined(__riscv__) + regs.sepc = regvalue; #endif break; case REG_SP: @@ -132,6 +138,8 @@ proc_regset(struct proc_handle *phdl, proc_reg_t reg, unsigned long regvalue) regs.r_regs[PC] = regvalue; #elif defined(__powerpc__) regs.fixreg[1] = regvalue; +#elif defined(__riscv__) + regs.sp = regvalue; #endif break; default: