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The AR71xx has APB interrupts in the MISC registers from 0-7, later

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chips have more.

So for now, let's allow more.  We should teach the apb code to just
reject interrupts that lie outside what the chip can do at runtime.
This commit is contained in:
Adrian Chadd 2014-03-16 08:39:46 +00:00
parent e581852dd5
commit 7afd1d0205
1 changed files with 6 additions and 4 deletions
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10
sys/mips/atheros/apbvar.h
View file

@ -23,21 +23,23 @@
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _APBVAR_H_
#define _APBVAR_H_
#define APB_IRQ_BASE 0
#define APB_IRQ_END 7
#define APB_NIRQS 8
#define APB_IRQ_END 31
#define APB_NIRQS 32
struct apb_softc {
struct rman apb_irq_rman;
struct rman apb_mem_rman;
/* IRQ events structs for child devices */
struct intr_event *sc_eventstab[APB_NIRQS];
mips_intrcnt_t sc_intr_counter[APB_NIRQS];
struct intr_event *sc_eventstab[APB_NIRQS];
mips_intrcnt_t sc_intr_counter[APB_NIRQS];
/* Resources and cookies for MIPS CPU INTs */
struct resource *sc_misc_irq;
void *sc_misc_ih;