From 7afd1d020504e6f189ee2109871ed11b9da52df5 Mon Sep 17 00:00:00 2001 From: Adrian Chadd Date: Sun, 16 Mar 2014 08:39:46 +0000 Subject: [PATCH] The AR71xx has APB interrupts in the MISC registers from 0-7, later chips have more. So for now, let's allow more. We should teach the apb code to just reject interrupts that lie outside what the chip can do at runtime. --- sys/mips/atheros/apbvar.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/sys/mips/atheros/apbvar.h b/sys/mips/atheros/apbvar.h index 2706034d254..f9af6ffa1bf 100644 --- a/sys/mips/atheros/apbvar.h +++ b/sys/mips/atheros/apbvar.h @@ -23,21 +23,23 @@ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. + * + * $FreeBSD$ */ #ifndef _APBVAR_H_ #define _APBVAR_H_ #define APB_IRQ_BASE 0 -#define APB_IRQ_END 7 -#define APB_NIRQS 8 +#define APB_IRQ_END 31 +#define APB_NIRQS 32 struct apb_softc { struct rman apb_irq_rman; struct rman apb_mem_rman; /* IRQ events structs for child devices */ - struct intr_event *sc_eventstab[APB_NIRQS]; - mips_intrcnt_t sc_intr_counter[APB_NIRQS]; + struct intr_event *sc_eventstab[APB_NIRQS]; + mips_intrcnt_t sc_intr_counter[APB_NIRQS]; /* Resources and cookies for MIPS CPU INTs */ struct resource *sc_misc_irq; void *sc_misc_ih;