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When ICW1 is issued the edge sense circuit is reset which means that

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following an initialization a low-to-high transistion is necesary to
generate an interrupt.

Reviewed by:	neel
This commit is contained in:
Tycho Nightingale 2015-03-06 02:05:45 +00:00
parent 8e01fdea2b
commit 76b3c718be
1 changed files with 1 additions and 0 deletions
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1
sys/amd64/vmm/io/vatpic.c
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@ -275,6 +275,7 @@ vatpic_icw1(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
atpic->ready = false;
atpic->icw_num = 1;
atpic->request = 0;
atpic->mask = 0;
atpic->lowprio = 7;
atpic->rd_cmd_reg = 0;