From 76b3c718be824fb13fae4e2e232ae2425ef81fd8 Mon Sep 17 00:00:00 2001
From: Tycho Nightingale <tychon@FreeBSD.org>
Date: Fri, 6 Mar 2015 02:05:45 +0000
Subject: [PATCH] When ICW1 is issued the edge sense circuit is reset which
 means that following an initialization a low-to-high transistion is necesary
 to generate an interrupt.

Reviewed by:	neel
---
 sys/amd64/vmm/io/vatpic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sys/amd64/vmm/io/vatpic.c b/sys/amd64/vmm/io/vatpic.c
index 328c35f700b..0df6e7c6808 100644
--- a/sys/amd64/vmm/io/vatpic.c
+++ b/sys/amd64/vmm/io/vatpic.c
@@ -275,6 +275,7 @@ vatpic_icw1(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
 	atpic->ready = false;
 
 	atpic->icw_num = 1;
+	atpic->request = 0;
 	atpic->mask = 0;
 	atpic->lowprio = 7;
 	atpic->rd_cmd_reg = 0;