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https://github.com/opnsense/src.git
synced 2026-05-28 04:12:45 -04:00
ice: Update to 1.42.5-k
- Removes duplicate E825C printout - Fixes a package download issue with E830 - Updates mentions of E830-XXV to E830-L - Fix FW logging on load issue by limiting the setting of FW log masks and other global configuration to just the first PF of the controller - Update ice_hw_autogen.h with timesync registers (unused in this driver) - Fix possible overflow condition in NVM access function - Blocks RDMA load on E830 devices Signed-off-by: Eric Joyner <erj@FreeBSD.org> Tested by: Jeffrey Pieper <jeffrey.e.pieper@intel.com> Relnotes: yes Sponsored by: Intel Corporation Differential Revision: https://reviews.freebsd.org/D46950 (cherry picked from commit 440addc642496f8d04fe17af9eb905ac4a5bdbd8)
This commit is contained in:
Eric Joyner
parent
5cf8640220
commit
5f92347a9b
10 changed files with 124 additions and 107 deletions
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@ -526,12 +526,13 @@ ice_download_pkg_sig_seg(struct ice_hw *hw, struct ice_sign_seg *seg)
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* @idx: segment index
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* @start: starting buffer
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* @count: buffer count
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* @last_seg: last segment being downloaded
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*
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* Note: idx must reference a ICE segment
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*/
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static enum ice_ddp_state
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ice_download_pkg_config_seg(struct ice_hw *hw, struct ice_pkg_hdr *pkg_hdr,
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u32 idx, u32 start, u32 count)
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u32 idx, u32 start, u32 count, bool last_seg)
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{
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struct ice_buf_table *bufs;
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enum ice_ddp_state state;
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@ -549,7 +550,7 @@ ice_download_pkg_config_seg(struct ice_hw *hw, struct ice_pkg_hdr *pkg_hdr,
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return ICE_DDP_PKG_ERR;
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state = ice_dwnld_cfg_bufs_no_lock(hw, bufs->buf_array, start, count,
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true);
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last_seg);
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return state;
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}
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@ -568,9 +569,11 @@ ice_dwnld_sign_and_cfg_segs(struct ice_hw *hw, struct ice_pkg_hdr *pkg_hdr,
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{
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enum ice_ddp_state state;
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struct ice_sign_seg *seg;
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bool last_seg = true;
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u32 conf_idx;
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u32 start;
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u32 count;
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u32 flags;
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seg = (struct ice_sign_seg *)ice_get_pkg_seg_by_idx(pkg_hdr, idx);
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if (!seg) {
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@ -581,6 +584,10 @@ ice_dwnld_sign_and_cfg_segs(struct ice_hw *hw, struct ice_pkg_hdr *pkg_hdr,
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conf_idx = LE32_TO_CPU(seg->signed_seg_idx);
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start = LE32_TO_CPU(seg->signed_buf_start);
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count = LE32_TO_CPU(seg->signed_buf_count);
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flags = LE32_TO_CPU(seg->flags);
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if (flags & ICE_SIGN_SEG_FLAGS_VALID)
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last_seg = !!(flags & ICE_SIGN_SEG_FLAGS_LAST);
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state = ice_download_pkg_sig_seg(hw, seg);
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if (state)
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@ -595,7 +602,7 @@ ice_dwnld_sign_and_cfg_segs(struct ice_hw *hw, struct ice_pkg_hdr *pkg_hdr,
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}
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state = ice_download_pkg_config_seg(hw, pkg_hdr, conf_idx, start,
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count);
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count, last_seg);
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exit:
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return state;
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@ -2321,6 +2328,22 @@ void ice_release_change_lock(struct ice_hw *hw)
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ice_release_res(hw, ICE_CHANGE_LOCK_RES_ID);
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}
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/**
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* ice_is_get_tx_sched_new_format
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* @hw: pointer to the HW struct
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*
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* Determines if the new format for the Tx scheduler get api is supported
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*/
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static bool
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ice_is_get_tx_sched_new_format(struct ice_hw *hw)
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{
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if (ice_is_e830(hw))
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return true;
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if (ice_is_e825c(hw))
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return true;
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return false;
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}
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/**
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* ice_get_set_tx_topo - get or set tx topology
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* @hw: pointer to the HW struct
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@ -2354,7 +2377,7 @@ ice_get_set_tx_topo(struct ice_hw *hw, u8 *buf, u16 buf_size,
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ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_tx_topo);
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cmd->get_flags = ICE_AQC_TX_TOPO_GET_RAM;
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if (!ice_is_e830(hw))
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if (!ice_is_get_tx_sched_new_format(hw))
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desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
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}
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@ -204,7 +204,10 @@ struct ice_sign_seg {
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__le32 signed_seg_idx;
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__le32 signed_buf_start;
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__le32 signed_buf_count;
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#define ICE_SIGN_SEG_RESERVED_COUNT 44
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#define ICE_SIGN_SEG_FLAGS_VALID 0x80000000
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#define ICE_SIGN_SEG_FLAGS_LAST 0x00000001
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__le32 flags;
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#define ICE_SIGN_SEG_RESERVED_COUNT 40
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u8 reserved[ICE_SIGN_SEG_RESERVED_COUNT];
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struct ice_buf_table buf_tbl;
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};
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@ -52,16 +52,16 @@
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#define ICE_DEV_ID_E830_SFP 0x12D3
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/* Intel(R) Ethernet Controller E830-C for backplane */
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#define ICE_DEV_ID_E830C_BACKPLANE 0x12D5
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/* Intel(R) Ethernet Controller E830-XXV for backplane */
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#define ICE_DEV_ID_E830_XXV_BACKPLANE 0x12DC
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/* Intel(R) Ethernet Controller E830-L for backplane */
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#define ICE_DEV_ID_E830_L_BACKPLANE 0x12DC
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/* Intel(R) Ethernet Controller E830-C for QSFP */
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#define ICE_DEV_ID_E830C_QSFP 0x12D8
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/* Intel(R) Ethernet Controller E830-XXV for QSFP */
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#define ICE_DEV_ID_E830_XXV_QSFP 0x12DD
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/* Intel(R) Ethernet Controller E830-L for QSFP */
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#define ICE_DEV_ID_E830_L_QSFP 0x12DD
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/* Intel(R) Ethernet Controller E830-C for SFP */
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#define ICE_DEV_ID_E830C_SFP 0x12DA
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/* Intel(R) Ethernet Controller E830-XXV for SFP */
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#define ICE_DEV_ID_E830_XXV_SFP 0x12DE
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/* Intel(R) Ethernet Controller E830-L for SFP */
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#define ICE_DEV_ID_E830_L_SFP 0x12DE
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/* Intel(R) Ethernet Controller E810-C for backplane */
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#define ICE_DEV_ID_E810C_BACKPLANE 0x1591
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/* Intel(R) Ethernet Controller E810-C for QSFP */
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@ -62,16 +62,16 @@
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* @var ice_rc_version
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* @brief driver release candidate version number
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*/
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const char ice_driver_version[] = "1.42.1-k";
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const char ice_driver_version[] = "1.42.5-k";
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const uint8_t ice_major_version = 1;
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const uint8_t ice_minor_version = 42;
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const uint8_t ice_patch_version = 1;
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const uint8_t ice_patch_version = 5;
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const uint8_t ice_rc_version = 0;
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#define PVIDV(vendor, devid, name) \
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PVID(vendor, devid, name " - 1.42.1-k")
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PVID(vendor, devid, name " - 1.42.5-k")
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#define PVIDV_OEM(vendor, devid, svid, sdevid, revid, name) \
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PVID_OEM(vendor, devid, svid, sdevid, revid, name " - 1.42.1-k")
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PVID_OEM(vendor, devid, svid, sdevid, revid, name " - 1.42.5-k")
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/**
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* @var ice_vendor_info_array
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@ -217,12 +217,12 @@ static const pci_vendor_info_t ice_vendor_info_array[] = {
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"Intel(R) Ethernet Connection E830-C for QSFP"),
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PVIDV(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830C_SFP,
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"Intel(R) Ethernet Connection E830-C for SFP"),
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PVIDV(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_XXV_BACKPLANE,
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"Intel(R) Ethernet Connection E830-XXV for backplane"),
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PVIDV(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_XXV_QSFP,
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"Intel(R) Ethernet Connection E830-XXV for QSFP"),
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PVIDV(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_XXV_SFP,
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"Intel(R) Ethernet Connection E830-XXV for SFP"),
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PVIDV(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_L_BACKPLANE,
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"Intel(R) Ethernet Connection E830-L for backplane"),
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PVIDV(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_L_QSFP,
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"Intel(R) Ethernet Connection E830-L for QSFP"),
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PVIDV(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E830_L_SFP,
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"Intel(R) Ethernet Connection E830-L for SFP"),
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PVIDV(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_BACKPLANE,
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"Intel(R) Ethernet Connection E825-C for backplane"),
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PVIDV(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_QSFP,
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@ -359,23 +359,6 @@ ice_add_fw_logging_tunables(struct ice_softc *sc, struct sysctl_oid *parent)
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"Firmware Logging");
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fwlog_list = SYSCTL_CHILDREN(fwlog_node);
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cfg->log_resolution = 10;
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SYSCTL_ADD_PROC(ctx, fwlog_list, OID_AUTO, "log_resolution",
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ICE_CTLFLAG_DEBUG | CTLTYPE_U8 | CTLFLAG_RWTUN, sc,
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0, ice_sysctl_fwlog_log_resolution,
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"CU", ICE_SYSCTL_HELP_FWLOG_LOG_RESOLUTION);
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cfg->options |= ICE_FWLOG_OPTION_ARQ_ENA;
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SYSCTL_ADD_PROC(ctx, fwlog_list, OID_AUTO, "arq_en",
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ICE_CTLFLAG_DEBUG | CTLTYPE_U8 | CTLFLAG_RWTUN, sc,
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ICE_FWLOG_OPTION_ARQ_ENA, ice_sysctl_fwlog_set_cfg_options,
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"CU", ICE_SYSCTL_HELP_FWLOG_ARQ_ENA);
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SYSCTL_ADD_PROC(ctx, fwlog_list, OID_AUTO, "uart_en",
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ICE_CTLFLAG_DEBUG | CTLTYPE_U8 | CTLFLAG_RWTUN, sc,
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ICE_FWLOG_OPTION_UART_ENA, ice_sysctl_fwlog_set_cfg_options,
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"CU", ICE_SYSCTL_HELP_FWLOG_UART_ENA);
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SYSCTL_ADD_PROC(ctx, fwlog_list, OID_AUTO, "on_load",
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ICE_CTLFLAG_DEBUG | CTLTYPE_U8 | CTLFLAG_RWTUN, sc,
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ICE_FWLOG_OPTION_REGISTER_ON_INIT, ice_sysctl_fwlog_set_cfg_options,
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@ -386,23 +369,43 @@ ice_add_fw_logging_tunables(struct ice_softc *sc, struct sysctl_oid *parent)
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0, ice_sysctl_fwlog_register,
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"CU", ICE_SYSCTL_HELP_FWLOG_REGISTER);
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module_node = SYSCTL_ADD_NODE(ctx, fwlog_list, OID_AUTO, "severity",
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ICE_CTLFLAG_DEBUG | CTLFLAG_RD, NULL,
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"Level of log output");
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hw->pf_id = ice_get_pf_id(hw);
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if (hw->pf_id == 0) {
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module_node = SYSCTL_ADD_NODE(ctx, fwlog_list, OID_AUTO, "severity",
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ICE_CTLFLAG_DEBUG | CTLFLAG_RD, NULL,
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"Level of log output");
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module_list = SYSCTL_CHILDREN(module_node);
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module_list = SYSCTL_CHILDREN(module_node);
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for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
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/* Setup some defaults */
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cfg->module_entries[i].module_id = i;
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cfg->module_entries[i].log_level = ICE_FWLOG_LEVEL_NONE;
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module = (enum ice_aqc_fw_logging_mod)i;
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for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
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/* Setup some defaults */
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cfg->module_entries[i].module_id = i;
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cfg->module_entries[i].log_level = ICE_FWLOG_LEVEL_NONE;
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module = (enum ice_aqc_fw_logging_mod)i;
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SYSCTL_ADD_PROC(ctx, module_list,
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OID_AUTO, ice_fw_module_str(module),
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ICE_CTLFLAG_DEBUG | CTLTYPE_STRING | CTLFLAG_RWTUN, sc,
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module, ice_sysctl_fwlog_module_log_severity,
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"A", ICE_SYSCTL_HELP_FWLOG_MODULE_SEVERITY);
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SYSCTL_ADD_PROC(ctx, module_list,
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OID_AUTO, ice_fw_module_str(module),
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ICE_CTLFLAG_DEBUG | CTLTYPE_STRING | CTLFLAG_RWTUN, sc,
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module, ice_sysctl_fwlog_module_log_severity,
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"A", ICE_SYSCTL_HELP_FWLOG_MODULE_SEVERITY);
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}
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cfg->log_resolution = 10;
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SYSCTL_ADD_PROC(ctx, fwlog_list, OID_AUTO, "log_resolution",
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ICE_CTLFLAG_DEBUG | CTLTYPE_U8 | CTLFLAG_RWTUN, sc,
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0, ice_sysctl_fwlog_log_resolution,
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"CU", ICE_SYSCTL_HELP_FWLOG_LOG_RESOLUTION);
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cfg->options |= ICE_FWLOG_OPTION_ARQ_ENA;
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SYSCTL_ADD_PROC(ctx, fwlog_list, OID_AUTO, "arq_en",
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ICE_CTLFLAG_DEBUG | CTLTYPE_U8 | CTLFLAG_RWTUN, sc,
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ICE_FWLOG_OPTION_ARQ_ENA, ice_sysctl_fwlog_set_cfg_options,
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"CU", ICE_SYSCTL_HELP_FWLOG_ARQ_ENA);
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SYSCTL_ADD_PROC(ctx, fwlog_list, OID_AUTO, "uart_en",
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ICE_CTLFLAG_DEBUG | CTLTYPE_U8 | CTLFLAG_RWTUN, sc,
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ICE_FWLOG_OPTION_UART_ENA, ice_sysctl_fwlog_set_cfg_options,
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"CU", ICE_SYSCTL_HELP_FWLOG_UART_ENA);
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}
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}
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@ -40,6 +40,20 @@
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#define PRTMAC_CTL_RX_PAUSE_ENABLE_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE)
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#define PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_S)
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#define PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_M : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_M)
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#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE(_i) (0x000FD000 + ((_i) * 64)) /* _i=0...7 */ /* Reset Source: CORER */
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#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_MAX_INDEX 7
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#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_START_S 0
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#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_START_M MAKEMASK(0x3F, 0)
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#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_END_S 6
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#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_END_M MAKEMASK(0x3F, 6)
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#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_VM_VF_TYPE_S 12
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#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_VM_VF_TYPE_M MAKEMASK(0x3, 12)
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#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_VM_VF_NUM_S 14
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#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_VM_VF_NUM_M MAKEMASK(0x3FF, 14)
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#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_PF_NUM_S 24
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#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_PF_NUM_M MAKEMASK(0x7, 24)
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#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_ENABLE_S 31
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#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_ENABLE_M BIT(31)
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#define GL_HIDA(_i) (0x00082000 + ((_i) * 4))
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#define GL_HIBA(_i) (0x00081000 + ((_i) * 4))
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#define GL_HICR 0x00082040
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@ -11875,44 +11875,6 @@ ice_sysctl_allow_no_fec_mod_in_auto(SYSCTL_HANDLER_ARGS)
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return (0);
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}
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/**
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* ice_print_dual_nac_info - Print NAC status/ID information
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* @sc: device softc structure
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*
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* Prints out information about the NAC mode if the device is capable of
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* being part of a system with multiple NACs.
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*
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* @pre Must be called after ice_init_hw() and ice_init_device_features()
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* sometime during driver load.
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*/
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void
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ice_print_dual_nac_info(struct ice_softc *sc)
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{
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struct ice_hw *hw = &sc->hw;
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device_t dev = sc->dev;
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bool is_dual_nac, is_primary_nac;
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u8 cpk_id;
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is_dual_nac = (hw->dev_caps.nac_topo.mode & ICE_NAC_TOPO_DUAL_M);
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is_primary_nac = (hw->dev_caps.nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M);
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cpk_id = hw->dev_caps.nac_topo.id;
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if (ice_is_bit_set(sc->feat_cap, ICE_FEATURE_DUAL_NAC)) {
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log(LOG_INFO, "%s: In %s NAC mode\n",
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device_get_nameunit(dev),
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is_dual_nac ? "Dual" : "Single");
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if (is_dual_nac) {
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ice_set_bit(ICE_FEATURE_DUAL_NAC, sc->feat_en);
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log(LOG_INFO,
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"%s: PF is configured in %s mode with IP instance ID %u\n",
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device_get_nameunit(dev),
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is_primary_nac ? "primary" : "secondary",
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cpk_id);
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}
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}
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}
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/**
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* ice_sysctl_temperature - Retrieve NIC temp via AQ command
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* @oidp: sysctl oid structure
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@ -1010,7 +1010,6 @@ void ice_init_health_events(struct ice_softc *sc);
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void ice_cfg_pba_num(struct ice_softc *sc);
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int ice_handle_debug_dump_ioctl(struct ice_softc *sc, struct ifdrv *ifd);
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u8 ice_dcb_get_tc_map(const struct ice_dcbx_cfg *dcbcfg);
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void ice_print_dual_nac_info(struct ice_softc *sc);
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void ice_do_dcb_reconfig(struct ice_softc *sc, bool pending_mib);
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||||
int ice_setup_vsi_mirroring(struct ice_vsi *vsi);
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||||
|
||||
|
|
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|||
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|
@ -711,6 +711,8 @@ int ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
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|||
return status;
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||||
}
|
||||
|
||||
#define check_add_overflow __builtin_add_overflow
|
||||
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||||
/**
|
||||
* ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
|
||||
* @hw: pointer to hardware structure
|
||||
|
|
@ -726,8 +728,7 @@ int
|
|||
ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
|
||||
u16 module_type)
|
||||
{
|
||||
u16 pfa_len, pfa_ptr;
|
||||
u32 next_tlv;
|
||||
u16 pfa_len, pfa_ptr, next_tlv, max_tlv;
|
||||
int status;
|
||||
|
||||
status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
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||||
|
|
@ -740,11 +741,23 @@ ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
|
|||
ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
|
||||
return status;
|
||||
}
|
||||
/* Starting with first TLV after PFA length, iterate through the list
|
||||
|
||||
if (check_add_overflow(pfa_ptr, (u16)(pfa_len - 1), &max_tlv)) {
|
||||
ice_debug(hw, ICE_DBG_INIT, "PFA starts at offset %u. PFA length of %u caused 16-bit arithmetic overflow.\n",
|
||||
pfa_ptr, pfa_len);
|
||||
return ICE_ERR_INVAL_SIZE;
|
||||
}
|
||||
|
||||
/* The Preserved Fields Area contains a sequence of TLVs which define
|
||||
* its contents. The PFA length includes all of the TLVs, plus its
|
||||
* initial length word itself, *and* one final word at the end of all
|
||||
* of the TLVs.
|
||||
*
|
||||
* Starting with first TLV after PFA length, iterate through the list
|
||||
* of TLVs to find the requested one.
|
||||
*/
|
||||
next_tlv = pfa_ptr + 1;
|
||||
while (next_tlv < ((u32)pfa_ptr + pfa_len)) {
|
||||
while (next_tlv < max_tlv) {
|
||||
u16 tlv_sub_module_type;
|
||||
u16 tlv_len;
|
||||
|
||||
|
|
@ -761,10 +774,6 @@ ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
|
|||
ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
|
||||
break;
|
||||
}
|
||||
if (tlv_len > pfa_len) {
|
||||
ice_debug(hw, ICE_DBG_INIT, "Invalid TLV length.\n");
|
||||
return ICE_ERR_INVAL_SIZE;
|
||||
}
|
||||
if (tlv_sub_module_type == module_type) {
|
||||
if (tlv_len) {
|
||||
*module_tlv = (u16)next_tlv;
|
||||
|
|
@ -773,10 +782,13 @@ ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
|
|||
}
|
||||
return ICE_ERR_INVAL_SIZE;
|
||||
}
|
||||
/* Check next TLV, i.e. current TLV pointer + length + 2 words
|
||||
* (for current TLV's type and length)
|
||||
*/
|
||||
next_tlv = next_tlv + tlv_len + 2;
|
||||
|
||||
if (check_add_overflow(next_tlv, (u16)2, &next_tlv) ||
|
||||
check_add_overflow(next_tlv, tlv_len, &next_tlv)) {
|
||||
ice_debug(hw, ICE_DBG_INIT, "TLV of type %u and length 0x%04x caused 16-bit arithmetic overflow. The PFA starts at 0x%04x and has length of 0x%04x\n",
|
||||
tlv_sub_module_type, tlv_len, pfa_ptr, pfa_len);
|
||||
return ICE_ERR_INVAL_SIZE;
|
||||
}
|
||||
}
|
||||
/* Module does not exist */
|
||||
return ICE_ERR_DOES_NOT_EXIST;
|
||||
|
|
|
|||
|
|
@ -539,8 +539,6 @@ reinit_hw:
|
|||
|
||||
ice_init_device_features(sc);
|
||||
|
||||
ice_print_dual_nac_info(sc);
|
||||
|
||||
/* Keep flag set by default */
|
||||
ice_set_state(&sc->state, ICE_STATE_LINK_ACTIVE_ON_DOWN);
|
||||
|
||||
|
|
@ -2605,7 +2603,9 @@ ice_rebuild(struct ice_softc *sc)
|
|||
}
|
||||
|
||||
/* Re-enable FW logging. Keep going even if this fails */
|
||||
status = ice_fwlog_set(hw, &hw->fwlog_cfg);
|
||||
status = ICE_SUCCESS;
|
||||
if (hw->pf_id == 0)
|
||||
status = ice_fwlog_set(hw, &hw->fwlog_cfg);
|
||||
if (!status) {
|
||||
/*
|
||||
* We should have the most updated cached copy of the
|
||||
|
|
@ -2901,7 +2901,8 @@ ice_init_device_features(struct ice_softc *sc)
|
|||
/* Disable features due to hardware limitations... */
|
||||
if (!hw->func_caps.common_cap.rss_table_size)
|
||||
ice_clear_bit(ICE_FEATURE_RSS, sc->feat_cap);
|
||||
if (!hw->func_caps.common_cap.iwarp || !ice_enable_irdma)
|
||||
if (!hw->func_caps.common_cap.iwarp || !ice_enable_irdma ||
|
||||
ice_is_e830(hw))
|
||||
ice_clear_bit(ICE_FEATURE_RDMA, sc->feat_cap);
|
||||
if (!hw->func_caps.common_cap.dcb)
|
||||
ice_clear_bit(ICE_FEATURE_DCB, sc->feat_cap);
|
||||
|
|
|
|||
Loading…
Reference in a new issue