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Set C1 "I/O then Halt" capability bit for Intel EIST. Some broken BIOSes

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refuse to load external SSDTs if this bit is unset for _PDC.  It seems Linux
and OpenSolaris did the same long ago.

MFC after:	1 week
This commit is contained in:
Jung-uk Kim 2011-02-25 23:14:24 +00:00
parent 339f34e3a0
commit 49abdda9b7
1 changed files with 5 additions and 2 deletions
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7
sys/x86/cpufreq/est.c
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@ -947,8 +947,11 @@ static int
est_features(driver_t *driver, u_int *features)
{
/* Notify the ACPI CPU that we support direct access to MSRs */
*features = ACPI_CAP_PERF_MSRS;
/*
* Notify the ACPI CPU that we support direct access to MSRs.
* XXX C1 "I/O then Halt" seems necessary for some broken BIOS.
*/
*features = ACPI_CAP_PERF_MSRS | ACPI_CAP_C1_IO_HALT;
return (0);
}