From 49abdda9b79728ff8f9a8da3c10dcfdc29e921cb Mon Sep 17 00:00:00 2001 From: Jung-uk Kim Date: Fri, 25 Feb 2011 23:14:24 +0000 Subject: [PATCH] Set C1 "I/O then Halt" capability bit for Intel EIST. Some broken BIOSes refuse to load external SSDTs if this bit is unset for _PDC. It seems Linux and OpenSolaris did the same long ago. MFC after: 1 week --- sys/x86/cpufreq/est.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/sys/x86/cpufreq/est.c b/sys/x86/cpufreq/est.c index ecca30cf59d..678efb610c4 100644 --- a/sys/x86/cpufreq/est.c +++ b/sys/x86/cpufreq/est.c @@ -947,8 +947,11 @@ static int est_features(driver_t *driver, u_int *features) { - /* Notify the ACPI CPU that we support direct access to MSRs */ - *features = ACPI_CAP_PERF_MSRS; + /* + * Notify the ACPI CPU that we support direct access to MSRs. + * XXX C1 "I/O then Halt" seems necessary for some broken BIOS. + */ + *features = ACPI_CAP_PERF_MSRS | ACPI_CAP_C1_IO_HALT; return (0); }