Konstantin Belousov c30578feeb Provide part of the mitigation for L1TF-VMM. ... On the guest entry in bhyve, flush L1 data cache, using either L1D flush command MSR if available, or by reading enough uninteresting data to fill whole cache. Flush is automatically enabled on CPUs which do not report RDCL_NO, and can be disabled with the hw.vmm.l1d_flush tunable/kenv. Security: CVE-2018-3646 Reviewed by: emaste. jhb, Tony Luck <tony.luck@intel.com> Sponsored by: The FreeBSD Foundation		2018-08-14 17:29:41 +00:00
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acpica	Rename assym.s to assym.inc	2018-03-20 17:58:51 +00:00
amd64	Reserve page at the physical address zero on amd64.	2018-08-14 17:14:33 +00:00
cloudabi32	Use TO_PTR() to convert integers to pointers.	2017-11-26 14:45:56 +00:00
cloudabi64	Use TO_PTR() to convert integers to pointers.	2017-11-26 14:45:56 +00:00
conf	COMPAT_LINUX32 has not depended on COMPAT_43 in some time.	2018-07-31 21:40:13 +00:00
ia32	Use SMAP on amd64.	2018-07-29 20:47:00 +00:00
include	amd64: ensure that curproc->p_vmspace pmap always matches PCPU	2018-08-14 16:37:14 +00:00
linux	Futex support functions in linux.ko and linux32.ko on amd64 should be	2018-08-07 18:29:10 +00:00
linux32	Futex support functions in linux.ko and linux32.ko on amd64 should be	2018-08-07 18:29:10 +00:00
pci	sys/amd64: further adoption of SPDX licensing ID tags.	2017-11-27 15:03:07 +00:00
sgx	Rename assym.s to assym.inc	2018-03-20 17:58:51 +00:00
vmm	Provide part of the mitigation for L1TF-VMM.	2018-08-14 17:29:41 +00:00
Makefile	Bring the tags and links entries for amd64 up to date.	2015-10-27 22:59:24 +00:00