mirror of
https://github.com/opnsense/src.git
synced 2026-02-24 18:30:55 -05:00
In n32 and n64, add support for physical address above 4GB by having 64 bit page table entries and physical addresses. Major changes are: - param.h: update PTE sizes, masks and shift values to support 64 bit PTEs. - param.h: remove DELAY(), mips_btop(same as atop), mips_ptob (same as ptoa), and reformat. - param.h: remove casting to unsigned long in trunc_page and round_page since this will be used on physical addresses. - _types.h: have 64 bit __vm_paddr_t for n32. - pte.h: update TLB LO0/1 access macros to support 64 bit PTE - pte.h: assembly macros for PTE operations. - proc.h: md_upte is now 64 bit for n32 and n64. - exception.S and swtch.S: use the new PTE macros for PTE operations. - cpufunc.h: TLB_LO0/1 registers are 64bit for n32 and n64. - xlr_machdep.c: Add memory segments above 4GB to phys_avail[] as they are supported now. Reviewed by: jmallett (earlier version) |
||
|---|---|---|
| .. | ||
| adm5120 | ||
| alchemy | ||
| atheros | ||
| cavium | ||
| compile | ||
| conf | ||
| idt | ||
| include | ||
| malta | ||
| mips | ||
| rmi | ||
| sentry5 | ||
| sibyte | ||