Andriy Gapon e5e4452078 ensure that initial local apic id is sane on AMD 10h systems ... Summary: The Initial Local APIC ID is returned by CPUID function 1 (in EBX). On AMD Family 10h systems the way that ID is built is controlled by an MSR bit (InitApicIdCpuIdLo). BKDG instructs BIOS to set it in a certain way, but a BIOS can be buggy. In that case the ID can confuse tools that use it, e.g. hwloc. For example, on a system that I own real Local APIC IDs are configured as 0, 1, 2, 3, but IDs reported via CPUID.1 are 0, 0x40, 0x80, 0xc0. See: https://github.com/open-mpi/hwloc/issues/183 Reviewed by: kib MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D6060		2016-04-28 08:29:57 +00:00
..
acpica	If x86 CPU implementation of the MWAIT instruction reasonably	2015-05-09 12:28:48 +00:00
amd64	ensure that initial local apic id is sane on AMD 10h systems	2016-04-28 08:29:57 +00:00
cloudabi64	Make CloudABI's way of doing TLS more friendly to userspace emulators.	2016-04-06 11:11:31 +00:00
conf	hyperv: Deprecate HYPERV option by moving Hyper-V IDT vector into vmbus	2016-04-15 02:20:18 +00:00
ia32	Convert ss_sp in stack_t and sigstack to void *.	2016-01-27 17:55:01 +00:00
include	Enable DEVICE_NUMA with up to 8 domains by default on amd64.	2016-04-12 21:23:44 +00:00
linux	Cleanup redundant parenthesis from existing howmany()/roundup() macro uses.	2016-04-22 16:57:42 +00:00
linux32	Cleanup redundant parenthesis from existing howmany()/roundup() macro uses.	2016-04-22 16:57:42 +00:00
pci	Pull in r267961 and r267973 again. Fix for issues reported will follow.	2014-06-28 03:56:17 +00:00
vmm	Allow guest writes to AMD microcode update[0xc0010020] MSR without updating actual hardware MSR. This allows guest microcode update to go through which otherwise failing because wrmsr() was returning EINVAL.	2016-04-11 05:09:43 +00:00
Makefile	Bring the tags and links entries for amd64 up to date.	2015-10-27 22:59:24 +00:00