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251 lines
7.5 KiB
C
251 lines
7.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <mips/nlm/hal/mips-extns.h>
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#include <mips/nlm/hal/haldefs.h>
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#include <mips/nlm/hal/iomap.h>
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#include <mips/nlm/hal/sys.h>
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#include <mips/nlm/hal/nae.h>
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#include <mips/nlm/hal/mdio.h>
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#include <mips/nlm/hal/sgmii.h>
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#include <mips/nlm/hal/xaui.h>
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#include <mips/nlm/xlp.h>
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void
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nlm_xaui_pcs_init(uint64_t nae_base, int xaui_cplx_mask)
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{
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int block, lane_ctrl, reg;
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int cplx_lane_enable;
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int lane_enable = 0;
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uint32_t regval;
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cplx_lane_enable = LM_XAUI |
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(LM_XAUI << 4) |
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(LM_XAUI << 8) |
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(LM_XAUI << 12);
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if (xaui_cplx_mask == 0)
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return;
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/* write 0x2 to enable SGMII for all lane */
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block = 7;
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if (xaui_cplx_mask & 0x3) { /* Complexes 0, 1 */
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lane_enable = nlm_read_nae_reg(nae_base,
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NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_0_1));
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if (xaui_cplx_mask & 0x1) { /* Complex 0 */
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lane_enable &= ~(0xFFFF);
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lane_enable |= cplx_lane_enable;
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}
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if (xaui_cplx_mask & 0x2) { /* Complex 1 */
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lane_enable &= ~(0xFFFF<<16);
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lane_enable |= (cplx_lane_enable << 16);
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}
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_0_1),
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lane_enable);
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}
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lane_enable = 0;
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if (xaui_cplx_mask & 0xc) { /* Complexes 2, 3 */
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lane_enable = nlm_read_nae_reg(nae_base,
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NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_2_3));
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if (xaui_cplx_mask & 0x4) { /* Complex 2 */
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lane_enable &= ~(0xFFFF);
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lane_enable |= cplx_lane_enable;
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}
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if (xaui_cplx_mask & 0x8) { /* Complex 3 */
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lane_enable &= ~(0xFFFF<<16);
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lane_enable |= (cplx_lane_enable << 16);
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}
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_2_3),
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lane_enable);
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}
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/* Bring txpll out of reset */
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for (block = 0; block < 4; block++) {
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if ((xaui_cplx_mask & (1 << block)) == 0)
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continue;
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for (lane_ctrl = PHY_LANE_0_CTRL;
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lane_ctrl <= PHY_LANE_3_CTRL; lane_ctrl++) {
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if (!nlm_is_xlp8xx_ax())
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xlp_nae_lane_reset_txpll(nae_base,
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block, lane_ctrl, PHYMODE_XAUI);
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else
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xlp_ax_nae_lane_reset_txpll(nae_base, block,
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lane_ctrl, PHYMODE_XAUI);
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}
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}
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/* Wait for Rx & TX clock stable */
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for (block = 0; block < 4; block++) {
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if ((xaui_cplx_mask & (1 << block)) == 0)
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continue;
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for (lane_ctrl = PHY_LANE_0_CTRL;
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lane_ctrl <= PHY_LANE_3_CTRL; lane_ctrl++) {
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reg = NAE_REG(block, PHY, lane_ctrl - 4);
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/* Wait for TX clock to be set */
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do {
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regval = nlm_read_nae_reg(nae_base, reg);
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} while ((regval & LANE_TX_CLK) == 0);
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/* Wait for RX clock to be set */
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do {
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regval = nlm_read_nae_reg(nae_base, reg);
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} while ((regval & LANE_RX_CLK) == 0);
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/* Wait for XAUI Lane fault to be cleared */
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do {
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regval = nlm_read_nae_reg(nae_base, reg);
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} while ((regval & XAUI_LANE_FAULT) != 0);
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}
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}
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}
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void
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nlm_nae_setup_rx_mode_xaui(uint64_t base, int nblock, int iface, int port_type,
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int broadcast_en, int multicast_en, int pause_en, int promisc_en)
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{
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uint32_t val;
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val = ((broadcast_en & 0x1) << 10) |
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((pause_en & 0x1) << 9) |
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((multicast_en & 0x1) << 8) |
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((promisc_en & 0x1) << 7) | /* unicast_enable - enables promisc mode */
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1; /* MAC address is always valid */
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nlm_write_nae_reg(base, XAUI_MAC_FILTER_CFG(nblock), val);
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}
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void
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nlm_nae_setup_mac_addr_xaui(uint64_t base, int nblock, int iface,
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int port_type, unsigned char *mac_addr)
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{
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nlm_write_nae_reg(base,
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XAUI_MAC_ADDR0_LO(nblock),
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(mac_addr[5] << 24) |
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(mac_addr[4] << 16) |
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(mac_addr[3] << 8) |
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mac_addr[2]);
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nlm_write_nae_reg(base,
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XAUI_MAC_ADDR0_HI(nblock),
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(mac_addr[1] << 24) |
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(mac_addr[0] << 16));
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nlm_write_nae_reg(base,
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XAUI_MAC_ADDR_MASK0_LO(nblock),
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0xffffffff);
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nlm_write_nae_reg(base,
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XAUI_MAC_ADDR_MASK0_HI(nblock),
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0xffffffff);
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nlm_nae_setup_rx_mode_xaui(base, nblock, iface,
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XAUIC,
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1, /* broadcast enabled */
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1, /* multicast enabled */
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0, /* do not accept pause frames */
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0 /* promisc mode disabled */
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);
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}
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void
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nlm_config_xaui_mtu(uint64_t nae_base, int nblock,
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int max_tx_frame_sz, int max_rx_frame_sz)
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{
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uint32_t tx_words = max_tx_frame_sz >> 2; /* max_tx_frame_sz / 4 */
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/* write max frame length */
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nlm_write_nae_reg(nae_base,
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XAUI_MAX_FRAME_LEN(nblock),
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((tx_words & 0x3ff) << 16) | (max_rx_frame_sz & 0xffff));
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}
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void
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nlm_config_xaui(uint64_t nae_base, int nblock,
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int max_tx_frame_sz, int max_rx_frame_sz, int vlan_pri_en)
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{
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uint32_t val;
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val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
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val &= ~(0x1 << 11); /* clear soft reset */
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nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val);
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val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
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val &= ~(0x3 << 11); /* clear soft reset and hard reset */
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nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val);
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nlm_write_nae_reg(nae_base, XAUI_CONFIG0(nblock), 0xffffffff);
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nlm_write_nae_reg(nae_base, XAUI_CONFIG0(nblock), 0);
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/* Enable tx/rx frame */
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val = 0x000010A8;
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val |= XAUI_CONFIG_LENCHK;
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val |= XAUI_CONFIG_GENFCS;
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val |= XAUI_CONFIG_PAD_64;
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nlm_write_nae_reg(nae_base, XAUI_CONFIG1(nblock), val);
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/* write max frame length */
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nlm_config_xaui_mtu(nae_base, nblock, max_tx_frame_sz,
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max_rx_frame_sz);
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/* set stats counter */
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val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
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val |= (0x1 << NETIOR_XGMAC_VLAN_DC_POS);
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val |= (0x1 << NETIOR_XGMAC_STATS_EN_POS);
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if (vlan_pri_en) {
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val |= (0x1 << NETIOR_XGMAC_TX_PFC_EN_POS);
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val |= (0x1 << NETIOR_XGMAC_RX_PFC_EN_POS);
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val |= (0x1 << NETIOR_XGMAC_TX_PAUSE_POS);
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} else {
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val &= ~(0x1 << NETIOR_XGMAC_TX_PFC_EN_POS);
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val |= (0x1 << NETIOR_XGMAC_TX_PAUSE_POS);
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}
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nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val);
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/* configure on / off timer */
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if (vlan_pri_en)
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val = 0xF1230000; /* PFC mode, offtimer = 0xf123, ontimer = 0 */
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else
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val = 0x0000F123; /* link level FC mode, offtimer = 0xf123 */
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nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL2(nblock), val);
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/* set xaui tx threshold */
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val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL3(nblock));
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val &= ~(0x1f << 10);
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val |= ~(15 << 10);
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nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL3(nblock), val);
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}
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