Ruslan Bukin c214a270f5 Allow setting access-width for UART registers. ... This is required for FDT's standard "reg-io-width" property (similar to "reg-shift" property) found in many DTS files. This fixes operation on Altera Arria 10 SOC Development Kit, where standard ns8250 uart allows 4-byte access only. Reviewed by: kan, marcel Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D9785		2017-02-27 20:08:42 +00:00
..
alchemy_machdep.c	Merge from vmobj-rwlock branch:	2013-02-26 01:00:11 +00:00
aureg.h
files.alchemy	With this commit our friend RMI will now compile. I have	2009-10-30 08:53:11 +00:00
obio.c	Remove NULL checks after M_WAITOK allocations from sys/mips/.	2016-05-11 09:42:24 +00:00
std.alchemy	o) Use ABI, not ISA_* options, to determine whether to compile bits if libkern	2012-03-12 21:25:32 +00:00
uart_bus_alchemy.c	Allow setting access-width for UART registers.	2017-02-27 20:08:42 +00:00
uart_cpu_alchemy.c	- Make mips_bus_space_generic be of type bus_space_tag_t instead of	2009-04-19 22:02:14 +00:00