mirror of
https://github.com/opnsense/src.git
synced 2026-04-21 14:17:06 -04:00
97d40d3d4a
us up to version 2.17.50.20070703, at the last GPLv2 commit. Amongst others, this added upstream support for some FreeBSD-specific things that we previously had to manually hack in, such as the OSABI label support, and so on. There are also quite a number of new files, some for cpu's (e.g. SPU) that we may or may not be interested in, but those can be cleaned up later on, if needed.
182 lines
4.1 KiB
Text
182 lines
4.1 KiB
Text
// i386 register table.
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// Make %st first as we test for it.
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st, FloatReg|FloatAcc, 0, 0
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// 8 bit regs
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al, Reg8|Acc, 0, 0
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cl, Reg8|ShiftCount, 0, 1
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dl, Reg8, 0, 2
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bl, Reg8, 0, 3
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ah, Reg8, 0, 4
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ch, Reg8, 0, 5
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dh, Reg8, 0, 6
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bh, Reg8, 0, 7
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axl, Reg8|Acc, RegRex64, 0
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cxl, Reg8, RegRex64, 1
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dxl, Reg8, RegRex64, 2
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bxl, Reg8, RegRex64, 3
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spl, Reg8, RegRex64, 4
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bpl, Reg8, RegRex64, 5
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sil, Reg8, RegRex64, 6
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dil, Reg8, RegRex64, 7
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r8b, Reg8, RegRex|RegRex64, 0
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r9b, Reg8, RegRex|RegRex64, 1
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r10b, Reg8, RegRex|RegRex64, 2
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r11b, Reg8, RegRex|RegRex64, 3
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r12b, Reg8, RegRex|RegRex64, 4
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r13b, Reg8, RegRex|RegRex64, 5
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r14b, Reg8, RegRex|RegRex64, 6
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r15b, Reg8, RegRex|RegRex64, 7
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// 16 bit regs
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ax, Reg16|Acc, 0, 0
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cx, Reg16, 0, 1
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dx, Reg16|InOutPortReg, 0, 2
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bx, Reg16|BaseIndex, 0, 3
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sp, Reg16, 0, 4
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bp, Reg16|BaseIndex, 0, 5
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si, Reg16|BaseIndex, 0, 6
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di, Reg16|BaseIndex, 0, 7
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r8w, Reg16, RegRex, 0
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r9w, Reg16, RegRex, 1
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r10w, Reg16, RegRex, 2
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r11w, Reg16, RegRex, 3
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r12w, Reg16, RegRex, 4
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r13w, Reg16, RegRex, 5
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r14w, Reg16, RegRex, 6
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r15w, Reg16, RegRex, 7
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// 32 bit regs
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eax, Reg32|BaseIndex|Acc, 0, 0
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ecx, Reg32|BaseIndex, 0, 1
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edx, Reg32|BaseIndex, 0, 2
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ebx, Reg32|BaseIndex, 0, 3
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esp, Reg32, 0, 4
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ebp, Reg32|BaseIndex, 0, 5
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esi, Reg32|BaseIndex, 0, 6
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edi, Reg32|BaseIndex, 0, 7
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r8d, Reg32|BaseIndex, RegRex, 0
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r9d, Reg32|BaseIndex, RegRex, 1
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r10d, Reg32|BaseIndex, RegRex, 2
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r11d, Reg32|BaseIndex, RegRex, 3
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r12d, Reg32|BaseIndex, RegRex, 4
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r13d, Reg32|BaseIndex, RegRex, 5
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r14d, Reg32|BaseIndex, RegRex, 6
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r15d, Reg32|BaseIndex, RegRex, 7
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rax, Reg64|BaseIndex|Acc, 0, 0
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rcx, Reg64|BaseIndex, 0, 1
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rdx, Reg64|BaseIndex, 0, 2
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rbx, Reg64|BaseIndex, 0, 3
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rsp, Reg64, 0, 4
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rbp, Reg64|BaseIndex, 0, 5
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rsi, Reg64|BaseIndex, 0, 6
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rdi, Reg64|BaseIndex, 0, 7
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r8, Reg64|BaseIndex, RegRex, 0
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r9, Reg64|BaseIndex, RegRex, 1
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r10, Reg64|BaseIndex, RegRex, 2
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r11, Reg64|BaseIndex, RegRex, 3
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r12, Reg64|BaseIndex, RegRex, 4
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r13, Reg64|BaseIndex, RegRex, 5
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r14, Reg64|BaseIndex, RegRex, 6
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r15, Reg64|BaseIndex, RegRex, 7
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// Segment registers.
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es, SReg2, 0, 0
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cs, SReg2, 0, 1
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ss, SReg2, 0, 2
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ds, SReg2, 0, 3
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fs, SReg3, 0, 4
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gs, SReg3, 0, 5
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// Control registers.
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cr0, Control, 0, 0
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cr1, Control, 0, 1
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cr2, Control, 0, 2
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cr3, Control, 0, 3
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cr4, Control, 0, 4
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cr5, Control, 0, 5
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cr6, Control, 0, 6
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cr7, Control, 0, 7
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cr8, Control, RegRex, 0
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cr9, Control, RegRex, 1
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cr10, Control, RegRex, 2
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cr11, Control, RegRex, 3
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cr12, Control, RegRex, 4
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cr13, Control, RegRex, 5
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cr14, Control, RegRex, 6
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cr15, Control, RegRex, 7
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// Debug registers.
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db0, Debug, 0, 0
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db1, Debug, 0, 1
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db2, Debug, 0, 2
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db3, Debug, 0, 3
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db4, Debug, 0, 4
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db5, Debug, 0, 5
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db6, Debug, 0, 6
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db7, Debug, 0, 7
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db8, Debug, RegRex, 0
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db9, Debug, RegRex, 1
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db10, Debug, RegRex, 2
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db11, Debug, RegRex, 3
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db12, Debug, RegRex, 4
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db13, Debug, RegRex, 5
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db14, Debug, RegRex, 6
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db15, Debug, RegRex, 7
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dr0, Debug, 0, 0
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dr1, Debug, 0, 1
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dr2, Debug, 0, 2
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dr3, Debug, 0, 3
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dr4, Debug, 0, 4
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dr5, Debug, 0, 5
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dr6, Debug, 0, 6
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dr7, Debug, 0, 7
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dr8, Debug, RegRex, 0
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dr9, Debug, RegRex, 1
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dr10, Debug, RegRex, 2
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dr11, Debug, RegRex, 3
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dr12, Debug, RegRex, 4
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dr13, Debug, RegRex, 5
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dr14, Debug, RegRex, 6
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dr15, Debug, RegRex, 7
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// Test registers.
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tr0, Test, 0, 0
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tr1, Test, 0, 1
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tr2, Test, 0, 2
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tr3, Test, 0, 3
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tr4, Test, 0, 4
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tr5, Test, 0, 5
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tr6, Test, 0, 6
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tr7, Test, 0, 7
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// MMX and simd registers.
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mm0, RegMMX, 0, 0
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mm1, RegMMX, 0, 1
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mm2, RegMMX, 0, 2
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mm3, RegMMX, 0, 3
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mm4, RegMMX, 0, 4
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mm5, RegMMX, 0, 5
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mm6, RegMMX, 0, 6
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mm7, RegMMX, 0, 7
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xmm0, RegXMM, 0, 0
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xmm1, RegXMM, 0, 1
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xmm2, RegXMM, 0, 2
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xmm3, RegXMM, 0, 3
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xmm4, RegXMM, 0, 4
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xmm5, RegXMM, 0, 5
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xmm6, RegXMM, 0, 6
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xmm7, RegXMM, 0, 7
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xmm8, RegXMM, RegRex, 0
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xmm9, RegXMM, RegRex, 1
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xmm10, RegXMM, RegRex, 2
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xmm11, RegXMM, RegRex, 3
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xmm12, RegXMM, RegRex, 4
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xmm13, RegXMM, RegRex, 5
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xmm14, RegXMM, RegRex, 6
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xmm15, RegXMM, RegRex, 7
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// No type will make this register rejected for all purposes except
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// for addressing. This saves creating one extra type for RIP.
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rip, BaseIndex, 0, 0
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// fp regs.
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st(0), FloatReg|FloatAcc, 0, 0
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st(1), FloatReg, 0, 1
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st(2), FloatReg, 0, 2
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st(3), FloatReg, 0, 3
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st(4), FloatReg, 0, 4
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st(5), FloatReg, 0, 5
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st(6), FloatReg, 0, 6
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st(7), FloatReg, 0, 7
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