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Most of the changes are a direct result of adding thread awareness. Typically, DDB_REGS is gone. All registers are taken from the trapframe and backtraces use the PCB based contexts. DDB_REGS was defined to be a trapframe on all platforms anyway. Thread awareness introduces the following new commands: thread X switch to thread X (where X is the TID), show threads list all threads. The backtrace code has been made more flexible so that one can create backtraces for any thread by giving the thread ID as an argument to trace. With this change, ia64 has support for breakpoints.
452 lines
9.2 KiB
C
452 lines
9.2 KiB
C
/*
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* Mach Operating System
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* Copyright (c) 1992,1991,1990 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*
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* db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU)
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*/
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/*
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* Parts of this file are derived from Mach 3:
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*
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* File: alpha_instruction.c
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* Author: Alessandro Forin, Carnegie Mellon University
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* Date: 6/92
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*/
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/*
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* Interface to DDB.
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*
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* Modified for NetBSD/alpha by:
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*
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* Christopher G. Demetriou, Carnegie Mellon University
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*
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* Jason R. Thorpe, Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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/* __KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.2 1997/09/16 19:07:19 thorpej Exp $"); */
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/cons.h>
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#include <sys/kdb.h>
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#include <sys/kernel.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/smp.h>
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#include <vm/vm.h>
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#include <machine/db_machdep.h>
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#include <machine/pal.h>
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#include <machine/prom.h>
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#include <alpha/alpha/db_instruction.h>
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#include <ddb/ddb.h>
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#include <ddb/db_access.h>
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#include <ddb/db_sym.h>
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#include <ddb/db_variables.h>
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static db_varfcn_t db_frame;
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struct db_variable db_regs[] = {
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{ "v0", (db_expr_t *)FRAME_V0, db_frame },
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{ "t0", (db_expr_t *)FRAME_T0, db_frame },
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{ "t1", (db_expr_t *)FRAME_T1, db_frame },
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{ "t2", (db_expr_t *)FRAME_T2, db_frame },
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{ "t3", (db_expr_t *)FRAME_T3, db_frame },
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{ "t4", (db_expr_t *)FRAME_T4, db_frame },
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{ "t5", (db_expr_t *)FRAME_T5, db_frame },
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{ "t6", (db_expr_t *)FRAME_T6, db_frame },
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{ "t7", (db_expr_t *)FRAME_T7, db_frame },
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{ "s0", (db_expr_t *)FRAME_S0, db_frame },
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{ "s1", (db_expr_t *)FRAME_S1, db_frame },
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{ "s2", (db_expr_t *)FRAME_S2, db_frame },
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{ "s3", (db_expr_t *)FRAME_S3, db_frame },
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{ "s4", (db_expr_t *)FRAME_S4, db_frame },
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{ "s5", (db_expr_t *)FRAME_S5, db_frame },
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{ "s6", (db_expr_t *)FRAME_S6, db_frame },
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{ "a0", (db_expr_t *)FRAME_A0, db_frame },
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{ "a1", (db_expr_t *)FRAME_A1, db_frame },
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{ "a2", (db_expr_t *)FRAME_A2, db_frame },
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{ "a3", (db_expr_t *)FRAME_A3, db_frame },
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{ "a4", (db_expr_t *)FRAME_A4, db_frame },
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{ "a5", (db_expr_t *)FRAME_A5, db_frame },
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{ "t8", (db_expr_t *)FRAME_T8, db_frame },
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{ "t9", (db_expr_t *)FRAME_T9, db_frame },
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{ "t10", (db_expr_t *)FRAME_T10, db_frame },
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{ "t11", (db_expr_t *)FRAME_T11, db_frame },
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{ "ra", (db_expr_t *)FRAME_RA, db_frame },
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{ "t12", (db_expr_t *)FRAME_T12, db_frame },
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{ "at", (db_expr_t *)FRAME_AT, db_frame },
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{ "gp", (db_expr_t *)FRAME_GP, db_frame },
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{ "sp", (db_expr_t *)FRAME_SP, db_frame },
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{ "pc", (db_expr_t *)FRAME_PC, db_frame },
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{ "ps", (db_expr_t *)FRAME_PS, db_frame },
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{ "ai", (db_expr_t *)FRAME_T11, db_frame },
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{ "pv", (db_expr_t *)FRAME_T12, db_frame },
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};
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struct db_variable *db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]);
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static int
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db_frame(struct db_variable *vp, db_expr_t *valuep, int op)
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{
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if (kdb_frame == NULL)
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return (0);
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if (op == DB_VAR_GET)
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*valuep = kdb_frame->tf_regs[(uintptr_t)vp->valuep];
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else
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kdb_frame->tf_regs[(uintptr_t)vp->valuep] = *valuep;
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return (1);
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}
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/*
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* Read bytes from kernel address space for debugger.
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*/
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int
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db_read_bytes(vm_offset_t addr, size_t size, char *data)
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{
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jmp_buf jb;
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void *prev_jb;
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char *src;
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int ret;
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prev_jb = kdb_jmpbuf(jb);
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ret = setjmp(jb);
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if (ret == 0) {
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src = (char *)addr;
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while (size-- > 0)
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*data++ = *src++;
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}
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(void)kdb_jmpbuf(prev_jb);
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return (ret);
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}
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/*
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* Write bytes to kernel address space for debugger.
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*/
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int
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db_write_bytes(vm_offset_t addr, size_t size, char *data)
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{
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jmp_buf jb;
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void *prev_jb;
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char *dst;
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int ret;
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prev_jb = kdb_jmpbuf(jb);
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ret = setjmp(jb);
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if (ret == 0) {
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dst = (char *)addr;
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while (size-- > 0)
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*dst++ = *data++;
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alpha_pal_imb();
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}
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(void)kdb_jmpbuf(prev_jb);
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return (ret);
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}
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/*
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* Alpha-specific ddb commands:
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*
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* halt set halt bit in rpb and halt
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* reboot set reboot bit in rpb and halt
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*/
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DB_COMMAND(halt, db_mach_halt)
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{
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prom_halt(1);
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}
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DB_COMMAND(reboot, db_mach_reboot)
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{
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prom_halt(0);
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}
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/*
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* Map Alpha register numbers to trapframe/db_regs_t offsets.
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*/
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static int reg_to_frame[32] = {
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FRAME_V0,
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FRAME_T0,
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FRAME_T1,
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FRAME_T2,
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FRAME_T3,
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FRAME_T4,
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FRAME_T5,
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FRAME_T6,
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FRAME_T7,
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FRAME_S0,
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FRAME_S1,
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FRAME_S2,
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FRAME_S3,
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FRAME_S4,
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FRAME_S5,
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FRAME_S6,
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FRAME_A0,
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FRAME_A1,
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FRAME_A2,
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FRAME_A3,
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FRAME_A4,
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FRAME_A5,
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FRAME_T8,
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FRAME_T9,
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FRAME_T10,
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FRAME_T11,
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FRAME_RA,
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FRAME_T12,
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FRAME_AT,
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FRAME_GP,
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FRAME_SP,
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-1, /* zero */
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};
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u_long
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db_register_value(int regno)
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{
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if (regno > 31 || regno < 0) {
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db_printf(" **** STRANGE REGISTER NUMBER %d **** ", regno);
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return (0);
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}
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if (regno == 31)
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return (0);
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return (kdb_frame->tf_regs[reg_to_frame[regno]]);
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}
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/*
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* Support functions for software single-step.
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*/
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boolean_t
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db_inst_call(ins)
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int ins;
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{
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alpha_instruction insn;
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insn.bits = ins;
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return ((insn.branch_format.opcode == op_bsr) ||
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((insn.jump_format.opcode == op_j) &&
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(insn.jump_format.action & 1)));
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}
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boolean_t
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db_inst_return(ins)
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int ins;
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{
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alpha_instruction insn;
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insn.bits = ins;
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return ((insn.jump_format.opcode == op_j) &&
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(insn.jump_format.action == op_ret));
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}
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boolean_t
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db_inst_trap_return(ins)
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int ins;
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{
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alpha_instruction insn;
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insn.bits = ins;
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return ((insn.pal_format.opcode == op_pal) &&
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(insn.pal_format.function == PAL_OSF1_rti));
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}
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boolean_t
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db_inst_branch(ins)
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int ins;
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{
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alpha_instruction insn;
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insn.bits = ins;
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switch (insn.branch_format.opcode) {
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case op_j:
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case op_br:
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case op_fbeq:
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case op_fblt:
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case op_fble:
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case op_fbne:
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case op_fbge:
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case op_fbgt:
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case op_blbc:
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case op_beq:
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case op_blt:
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case op_ble:
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case op_blbs:
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case op_bne:
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case op_bge:
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case op_bgt:
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return (TRUE);
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}
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return (FALSE);
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}
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boolean_t
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db_inst_unconditional_flow_transfer(ins)
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int ins;
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{
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alpha_instruction insn;
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insn.bits = ins;
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switch (insn.branch_format.opcode) {
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case op_j:
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case op_br:
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return (TRUE);
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case op_pal:
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switch (insn.pal_format.function) {
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case PAL_OSF1_retsys:
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case PAL_OSF1_rti:
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case PAL_OSF1_callsys:
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return (TRUE);
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}
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}
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return (FALSE);
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}
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boolean_t
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db_inst_load(ins)
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int ins;
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{
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alpha_instruction insn;
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insn.bits = ins;
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/* Loads. */
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if (insn.mem_format.opcode == op_ldbu ||
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insn.mem_format.opcode == op_ldq_u ||
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insn.mem_format.opcode == op_ldwu)
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return (TRUE);
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if ((insn.mem_format.opcode >= op_ldf) &&
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(insn.mem_format.opcode <= op_ldt))
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return (TRUE);
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if ((insn.mem_format.opcode >= op_ldl) &&
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(insn.mem_format.opcode <= op_ldq_l))
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return (TRUE);
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/* Prefetches. */
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if (insn.mem_format.opcode == op_special) {
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/* Note: MB is treated as a store. */
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if ((insn.mem_format.displacement == (short)op_fetch) ||
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(insn.mem_format.displacement == (short)op_fetch_m))
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return (TRUE);
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}
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return (FALSE);
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}
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boolean_t
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db_inst_store(ins)
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int ins;
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{
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alpha_instruction insn;
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insn.bits = ins;
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/* Stores. */
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if (insn.mem_format.opcode == op_stw ||
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insn.mem_format.opcode == op_stb ||
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insn.mem_format.opcode == op_stq_u)
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return (TRUE);
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if ((insn.mem_format.opcode >= op_stf) &&
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(insn.mem_format.opcode <= op_stt))
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return (TRUE);
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if ((insn.mem_format.opcode >= op_stl) &&
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(insn.mem_format.opcode <= op_stq_c))
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return (TRUE);
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/* Barriers. */
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if (insn.mem_format.opcode == op_special) {
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if (insn.mem_format.displacement == op_mb)
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return (TRUE);
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}
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return (FALSE);
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}
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db_addr_t
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db_branch_taken(int ins, db_addr_t pc)
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{
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alpha_instruction insn;
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db_addr_t newpc;
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insn.bits = ins;
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switch (insn.branch_format.opcode) {
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/*
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* Jump format: target PC is (contents of instruction's "RB") & ~3.
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*/
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case op_j:
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newpc = db_register_value(insn.jump_format.rs) & ~3;
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break;
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/*
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* Branch format: target PC is
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* (new PC) + (4 * sign-ext(displacement)).
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*/
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case op_br:
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case op_fbeq:
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case op_fblt:
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case op_fble:
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case op_bsr:
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case op_fbne:
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case op_fbge:
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case op_fbgt:
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case op_blbc:
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case op_beq:
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case op_blt:
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case op_ble:
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case op_blbs:
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case op_bne:
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case op_bge:
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case op_bgt:
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newpc = (insn.branch_format.displacement << 2) + (pc + 4);
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break;
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default:
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printf("DDB: db_inst_branch_taken on non-branch!\n");
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newpc = pc; /* XXX */
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}
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return (newpc);
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}
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void
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db_show_mdpcpu(struct pcpu *pc)
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{
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db_printf("ipis = 0x%lx\n", pc->pc_pending_ipis);
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db_printf("next ASN = %d\n", pc->pc_next_asn);
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}
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