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013d817b53
This chipset suffered an (un)usual number of bugs and iterations. Let's add our NVM/firmware code from e1000 and the similar igc_nvm function from DPDK to keep track of issues. Sponsored by: BBOX.io (cherry picked from commit 33ed9bdca307bedb3d66a50ed7d4d7b4bf4acf39)
48 lines
1.4 KiB
C
48 lines
1.4 KiB
C
/*-
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* Copyright 2021 Intel Corp
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* Copyright 2021 Rubicon Communications, LLC (Netgate)
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _IGC_NVM_H_
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#define _IGC_NVM_H_
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struct igc_fw_version {
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u32 etrack_id;
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u16 eep_major;
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u16 eep_minor;
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u16 eep_build;
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u8 invm_major;
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u8 invm_minor;
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u8 invm_img_type;
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bool or_valid;
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u16 or_major;
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u16 or_build;
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u16 or_patch;
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};
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void igc_init_nvm_ops_generic(struct igc_hw *hw);
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s32 igc_null_read_nvm(struct igc_hw *hw, u16 a, u16 b, u16 *c);
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void igc_null_nvm_generic(struct igc_hw *hw);
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s32 igc_null_led_default(struct igc_hw *hw, u16 *data);
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s32 igc_null_write_nvm(struct igc_hw *hw, u16 a, u16 b, u16 *c);
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s32 igc_acquire_nvm_generic(struct igc_hw *hw);
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s32 igc_poll_eerd_eewr_done(struct igc_hw *hw, int ee_reg);
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s32 igc_read_mac_addr_generic(struct igc_hw *hw);
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s32 igc_read_pba_string_generic(struct igc_hw *hw, u8 *pba_num,
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u32 pba_num_size);
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s32 igc_read_nvm_eerd(struct igc_hw *hw, u16 offset, u16 words,
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u16 *data);
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s32 igc_valid_led_default_generic(struct igc_hw *hw, u16 *data);
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s32 igc_validate_nvm_checksum_generic(struct igc_hw *hw);
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s32 igc_write_nvm_spi(struct igc_hw *hw, u16 offset, u16 words,
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u16 *data);
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s32 igc_update_nvm_checksum_generic(struct igc_hw *hw);
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void igc_release_nvm_generic(struct igc_hw *hw);
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void igc_get_fw_version(struct igc_hw *hw,
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struct igc_fw_version *fw_vers);
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#endif
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