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1384 lines
29 KiB
C
1384 lines
29 KiB
C
/* $NetBSD: cache_mipsNN.c,v 1.10 2005/12/24 20:07:19 perry Exp $ */
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/*
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* SPDX-License-Identifier: BSD-4-Clause
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*
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* Copyright 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <sys/param.h>
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#include <machine/cache.h>
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#include <machine/cache_r4k.h>
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#include <machine/cpuinfo.h>
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#define round_line16(x) (((x) + 15) & ~15)
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#define trunc_line16(x) ((x) & ~15)
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#define round_line32(x) (((x) + 31) & ~31)
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#define trunc_line32(x) ((x) & ~31)
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#define round_line64(x) (((x) + 63) & ~63)
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#define trunc_line64(x) ((x) & ~63)
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#define round_line128(x) (((x) + 127) & ~127)
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#define trunc_line128(x) ((x) & ~127)
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#if defined(CPU_NLM)
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static __inline void
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xlp_sync(void)
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{
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__asm __volatile (
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".set push \n"
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".set noreorder \n"
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".set mips64 \n"
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"dla $8, 1f \n"
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"/* jr.hb $8 */ \n"
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".word 0x1000408 \n"
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"nop \n"
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"1: nop \n"
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".set pop \n"
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: : : "$8");
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}
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#endif
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#if defined(SB1250_PASS1)
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#define SYNC __asm volatile("sync; sync")
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#elif defined(CPU_NLM)
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#define SYNC xlp_sync()
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#else
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#define SYNC __asm volatile("sync")
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#endif
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#if defined(CPU_CNMIPS)
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#define SYNCI mips_sync_icache();
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#elif defined(CPU_NLM)
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#define SYNCI xlp_sync()
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#else
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#define SYNCI
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#endif
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/*
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* Exported variables for consumers like bus_dma code
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*/
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int mips_picache_linesize;
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int mips_pdcache_linesize;
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int mips_sdcache_linesize;
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int mips_dcache_max_linesize;
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static int picache_size;
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static int picache_stride;
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static int picache_loopcount;
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static int picache_way_mask;
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static int pdcache_size;
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static int pdcache_stride;
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static int pdcache_loopcount;
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static int pdcache_way_mask;
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static int sdcache_size;
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static int sdcache_stride;
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static int sdcache_loopcount;
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static int sdcache_way_mask;
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void
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mipsNN_cache_init(struct mips_cpuinfo * cpuinfo)
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{
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int flush_multiple_lines_per_way;
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flush_multiple_lines_per_way = cpuinfo->l1.ic_nsets * cpuinfo->l1.ic_linesize * cpuinfo->l1.ic_linesize > PAGE_SIZE;
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if (cpuinfo->icache_virtual) {
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/*
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* With a virtual Icache we don't need to flush
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* multiples of the page size with index ops; we just
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* need to flush one pages' worth.
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*/
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flush_multiple_lines_per_way = 0;
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}
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if (flush_multiple_lines_per_way) {
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picache_stride = PAGE_SIZE;
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picache_loopcount = (cpuinfo->l1.ic_nsets * cpuinfo->l1.ic_linesize / PAGE_SIZE) *
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cpuinfo->l1.ic_nways;
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} else {
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picache_stride = cpuinfo->l1.ic_nsets * cpuinfo->l1.ic_linesize;
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picache_loopcount = cpuinfo->l1.ic_nways;
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}
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if (cpuinfo->l1.dc_nsets * cpuinfo->l1.dc_linesize < PAGE_SIZE) {
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pdcache_stride = cpuinfo->l1.dc_nsets * cpuinfo->l1.dc_linesize;
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pdcache_loopcount = cpuinfo->l1.dc_nways;
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} else {
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pdcache_stride = PAGE_SIZE;
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pdcache_loopcount = (cpuinfo->l1.dc_nsets * cpuinfo->l1.dc_linesize / PAGE_SIZE) *
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cpuinfo->l1.dc_nways;
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}
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mips_picache_linesize = cpuinfo->l1.ic_linesize;
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mips_pdcache_linesize = cpuinfo->l1.dc_linesize;
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picache_size = cpuinfo->l1.ic_size;
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picache_way_mask = cpuinfo->l1.ic_nways - 1;
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pdcache_size = cpuinfo->l1.dc_size;
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pdcache_way_mask = cpuinfo->l1.dc_nways - 1;
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sdcache_stride = cpuinfo->l2.dc_nsets * cpuinfo->l2.dc_linesize;
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sdcache_loopcount = cpuinfo->l2.dc_nways;
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sdcache_size = cpuinfo->l2.dc_size;
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sdcache_way_mask = cpuinfo->l2.dc_nways - 1;
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mips_sdcache_linesize = cpuinfo->l2.dc_linesize;
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mips_dcache_max_linesize = MAX(mips_pdcache_linesize,
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mips_sdcache_linesize);
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#define CACHE_DEBUG
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#ifdef CACHE_DEBUG
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printf("Cache info:\n");
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if (cpuinfo->icache_virtual)
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printf(" icache is virtual\n");
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printf(" picache_stride = %d\n", picache_stride);
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printf(" picache_loopcount = %d\n", picache_loopcount);
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printf(" pdcache_stride = %d\n", pdcache_stride);
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printf(" pdcache_loopcount = %d\n", pdcache_loopcount);
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printf(" max line size = %d\n", mips_dcache_max_linesize);
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#endif
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}
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void
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mipsNN_icache_sync_all_16(void)
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{
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vm_offset_t va, eva;
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va = MIPS_PHYS_TO_KSEG0(0);
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eva = va + picache_size;
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/*
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* Since we're hitting the whole thing, we don't have to
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* worry about the N different "ways".
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*/
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mips_intern_dcache_wbinv_all();
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while (va < eva) {
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cache_r4k_op_32lines_16(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
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va += (32 * 16);
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}
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SYNC;
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}
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void
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mipsNN_icache_sync_all_32(void)
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{
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vm_offset_t va, eva;
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va = MIPS_PHYS_TO_KSEG0(0);
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eva = va + picache_size;
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/*
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* Since we're hitting the whole thing, we don't have to
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* worry about the N different "ways".
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*/
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mips_intern_dcache_wbinv_all();
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while (va < eva) {
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cache_r4k_op_32lines_32(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
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va += (32 * 32);
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}
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SYNC;
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}
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void
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mipsNN_icache_sync_all_64(void)
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{
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vm_offset_t va, eva;
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va = MIPS_PHYS_TO_KSEG0(0);
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eva = va + picache_size;
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/*
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* Since we're hitting the whole thing, we don't have to
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* worry about the N different "ways".
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*/
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mips_intern_dcache_wbinv_all();
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while (va < eva) {
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cache_r4k_op_32lines_64(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
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va += (32 * 64);
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}
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SYNC;
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}
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void
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mipsNN_icache_sync_range_16(vm_offset_t va, vm_size_t size)
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{
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vm_offset_t eva;
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eva = round_line16(va + size);
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va = trunc_line16(va);
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mips_intern_dcache_wb_range(va, (eva - va));
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while ((eva - va) >= (32 * 16)) {
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cache_r4k_op_32lines_16(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
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va += (32 * 16);
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}
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while (va < eva) {
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cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
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va += 16;
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}
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SYNC;
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}
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void
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mipsNN_icache_sync_range_32(vm_offset_t va, vm_size_t size)
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{
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vm_offset_t eva;
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eva = round_line32(va + size);
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va = trunc_line32(va);
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mips_intern_dcache_wb_range(va, (eva - va));
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while ((eva - va) >= (32 * 32)) {
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cache_r4k_op_32lines_32(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
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va += (32 * 32);
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}
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while (va < eva) {
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cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
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va += 32;
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}
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SYNC;
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}
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void
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mipsNN_icache_sync_range_64(vm_offset_t va, vm_size_t size)
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{
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vm_offset_t eva;
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eva = round_line64(va + size);
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va = trunc_line64(va);
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mips_intern_dcache_wb_range(va, (eva - va));
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while ((eva - va) >= (32 * 64)) {
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cache_r4k_op_32lines_64(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
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va += (32 * 64);
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}
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while (va < eva) {
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cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
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va += 64;
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}
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SYNC;
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}
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void
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mipsNN_icache_sync_range_index_16(vm_offset_t va, vm_size_t size)
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{
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vm_offset_t eva, tmpva;
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int i, stride, loopcount;
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/*
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* Since we're doing Index ops, we expect to not be able
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* to access the address we've been given. So, get the
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* bits that determine the cache index, and make a KSEG0
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* address out of them.
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*/
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va = MIPS_PHYS_TO_KSEG0(va & picache_way_mask);
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eva = round_line16(va + size);
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va = trunc_line16(va);
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/*
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* GCC generates better code in the loops if we reference local
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* copies of these global variables.
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*/
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stride = picache_stride;
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loopcount = picache_loopcount;
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mips_intern_dcache_wbinv_range_index(va, (eva - va));
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while ((eva - va) >= (8 * 16)) {
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tmpva = va;
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for (i = 0; i < loopcount; i++, tmpva += stride)
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cache_r4k_op_8lines_16(tmpva,
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CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
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va += 8 * 16;
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}
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while (va < eva) {
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tmpva = va;
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for (i = 0; i < loopcount; i++, tmpva += stride)
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cache_op_r4k_line(tmpva,
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CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
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va += 16;
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}
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}
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void
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mipsNN_icache_sync_range_index_32(vm_offset_t va, vm_size_t size)
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{
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vm_offset_t eva, tmpva;
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int i, stride, loopcount;
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/*
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* Since we're doing Index ops, we expect to not be able
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* to access the address we've been given. So, get the
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* bits that determine the cache index, and make a KSEG0
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* address out of them.
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*/
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va = MIPS_PHYS_TO_KSEG0(va & picache_way_mask);
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eva = round_line32(va + size);
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va = trunc_line32(va);
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/*
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* GCC generates better code in the loops if we reference local
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* copies of these global variables.
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*/
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stride = picache_stride;
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loopcount = picache_loopcount;
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mips_intern_dcache_wbinv_range_index(va, (eva - va));
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while ((eva - va) >= (8 * 32)) {
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tmpva = va;
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for (i = 0; i < loopcount; i++, tmpva += stride)
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cache_r4k_op_8lines_32(tmpva,
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CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
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va += 8 * 32;
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}
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while (va < eva) {
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tmpva = va;
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for (i = 0; i < loopcount; i++, tmpva += stride)
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cache_op_r4k_line(tmpva,
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CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
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va += 32;
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}
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}
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void
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mipsNN_icache_sync_range_index_64(vm_offset_t va, vm_size_t size)
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{
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vm_offset_t eva, tmpva;
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int i, stride, loopcount;
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|
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/*
|
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* Since we're doing Index ops, we expect to not be able
|
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* to access the address we've been given. So, get the
|
|
* bits that determine the cache index, and make a KSEG0
|
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* address out of them.
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*/
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va = MIPS_PHYS_TO_KSEG0(va & picache_way_mask);
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eva = round_line64(va + size);
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va = trunc_line64(va);
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/*
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* GCC generates better code in the loops if we reference local
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* copies of these global variables.
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*/
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stride = picache_stride;
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loopcount = picache_loopcount;
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mips_intern_dcache_wbinv_range_index(va, (eva - va));
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while ((eva - va) >= (8 * 64)) {
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tmpva = va;
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for (i = 0; i < loopcount; i++, tmpva += stride)
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cache_r4k_op_8lines_64(tmpva,
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CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
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va += 8 * 64;
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}
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while (va < eva) {
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tmpva = va;
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for (i = 0; i < loopcount; i++, tmpva += stride)
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cache_op_r4k_line(tmpva,
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CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
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va += 64;
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}
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}
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void
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mipsNN_pdcache_wbinv_all_16(void)
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{
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vm_offset_t va, eva;
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va = MIPS_PHYS_TO_KSEG0(0);
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eva = va + pdcache_size;
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/*
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* Since we're hitting the whole thing, we don't have to
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* worry about the N different "ways".
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*/
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while (va < eva) {
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cache_r4k_op_32lines_16(va,
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CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
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va += (32 * 16);
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}
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SYNC;
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}
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void
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mipsNN_pdcache_wbinv_all_32(void)
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{
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vm_offset_t va, eva;
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va = MIPS_PHYS_TO_KSEG0(0);
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eva = va + pdcache_size;
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/*
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* Since we're hitting the whole thing, we don't have to
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* worry about the N different "ways".
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*/
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while (va < eva) {
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cache_r4k_op_32lines_32(va,
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CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
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va += (32 * 32);
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}
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SYNC;
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}
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|
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void
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mipsNN_pdcache_wbinv_all_64(void)
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{
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vm_offset_t va, eva;
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va = MIPS_PHYS_TO_KSEG0(0);
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eva = va + pdcache_size;
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/*
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* Since we're hitting the whole thing, we don't have to
|
|
* worry about the N different "ways".
|
|
*/
|
|
|
|
while (va < eva) {
|
|
cache_r4k_op_32lines_64(va,
|
|
CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += (32 * 64);
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_wbinv_range_16(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva;
|
|
|
|
eva = round_line16(va + size);
|
|
va = trunc_line16(va);
|
|
|
|
while ((eva - va) >= (32 * 16)) {
|
|
cache_r4k_op_32lines_16(va,
|
|
CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
|
|
va += (32 * 16);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
|
|
va += 16;
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_wbinv_range_32(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva;
|
|
|
|
eva = round_line32(va + size);
|
|
va = trunc_line32(va);
|
|
|
|
while ((eva - va) >= (32 * 32)) {
|
|
cache_r4k_op_32lines_32(va,
|
|
CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
|
|
va += (32 * 32);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
|
|
va += 32;
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_wbinv_range_64(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva;
|
|
|
|
eva = round_line64(va + size);
|
|
va = trunc_line64(va);
|
|
|
|
while ((eva - va) >= (32 * 64)) {
|
|
cache_r4k_op_32lines_64(va,
|
|
CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
|
|
va += (32 * 64);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
|
|
va += 64;
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_wbinv_range_index_16(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva, tmpva;
|
|
int i, stride, loopcount;
|
|
|
|
/*
|
|
* Since we're doing Index ops, we expect to not be able
|
|
* to access the address we've been given. So, get the
|
|
* bits that determine the cache index, and make a KSEG0
|
|
* address out of them.
|
|
*/
|
|
va = MIPS_PHYS_TO_KSEG0(va & pdcache_way_mask);
|
|
|
|
eva = round_line16(va + size);
|
|
va = trunc_line16(va);
|
|
|
|
/*
|
|
* GCC generates better code in the loops if we reference local
|
|
* copies of these global variables.
|
|
*/
|
|
stride = pdcache_stride;
|
|
loopcount = pdcache_loopcount;
|
|
|
|
while ((eva - va) >= (8 * 16)) {
|
|
tmpva = va;
|
|
for (i = 0; i < loopcount; i++, tmpva += stride)
|
|
cache_r4k_op_8lines_16(tmpva,
|
|
CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += 8 * 16;
|
|
}
|
|
|
|
while (va < eva) {
|
|
tmpva = va;
|
|
for (i = 0; i < loopcount; i++, tmpva += stride)
|
|
cache_op_r4k_line(tmpva,
|
|
CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += 16;
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_wbinv_range_index_32(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva, tmpva;
|
|
int i, stride, loopcount;
|
|
|
|
/*
|
|
* Since we're doing Index ops, we expect to not be able
|
|
* to access the address we've been given. So, get the
|
|
* bits that determine the cache index, and make a KSEG0
|
|
* address out of them.
|
|
*/
|
|
va = MIPS_PHYS_TO_KSEG0(va & pdcache_way_mask);
|
|
|
|
eva = round_line32(va + size);
|
|
va = trunc_line32(va);
|
|
|
|
/*
|
|
* GCC generates better code in the loops if we reference local
|
|
* copies of these global variables.
|
|
*/
|
|
stride = pdcache_stride;
|
|
loopcount = pdcache_loopcount;
|
|
|
|
while ((eva - va) >= (8 * 32)) {
|
|
tmpva = va;
|
|
for (i = 0; i < loopcount; i++, tmpva += stride)
|
|
cache_r4k_op_8lines_32(tmpva,
|
|
CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += 8 * 32;
|
|
}
|
|
|
|
while (va < eva) {
|
|
tmpva = va;
|
|
for (i = 0; i < loopcount; i++, tmpva += stride)
|
|
cache_op_r4k_line(tmpva,
|
|
CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += 32;
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_wbinv_range_index_64(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva, tmpva;
|
|
int i, stride, loopcount;
|
|
|
|
/*
|
|
* Since we're doing Index ops, we expect to not be able
|
|
* to access the address we've been given. So, get the
|
|
* bits that determine the cache index, and make a KSEG0
|
|
* address out of them.
|
|
*/
|
|
va = MIPS_PHYS_TO_KSEG0(va & pdcache_way_mask);
|
|
|
|
eva = round_line64(va + size);
|
|
va = trunc_line64(va);
|
|
|
|
/*
|
|
* GCC generates better code in the loops if we reference local
|
|
* copies of these global variables.
|
|
*/
|
|
stride = pdcache_stride;
|
|
loopcount = pdcache_loopcount;
|
|
|
|
while ((eva - va) >= (8 * 64)) {
|
|
tmpva = va;
|
|
for (i = 0; i < loopcount; i++, tmpva += stride)
|
|
cache_r4k_op_8lines_64(tmpva,
|
|
CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += 8 * 64;
|
|
}
|
|
|
|
while (va < eva) {
|
|
tmpva = va;
|
|
for (i = 0; i < loopcount; i++, tmpva += stride)
|
|
cache_op_r4k_line(tmpva,
|
|
CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += 64;
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_inv_range_16(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva;
|
|
|
|
eva = round_line16(va + size);
|
|
va = trunc_line16(va);
|
|
|
|
while ((eva - va) >= (32 * 16)) {
|
|
cache_r4k_op_32lines_16(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
|
|
va += (32 * 16);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
|
|
va += 16;
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_inv_range_32(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva;
|
|
|
|
eva = round_line32(va + size);
|
|
va = trunc_line32(va);
|
|
|
|
while ((eva - va) >= (32 * 32)) {
|
|
cache_r4k_op_32lines_32(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
|
|
va += (32 * 32);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
|
|
va += 32;
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_inv_range_64(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva;
|
|
|
|
eva = round_line64(va + size);
|
|
va = trunc_line64(va);
|
|
|
|
while ((eva - va) >= (32 * 64)) {
|
|
cache_r4k_op_32lines_64(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
|
|
va += (32 * 64);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
|
|
va += 64;
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_wb_range_16(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva;
|
|
|
|
eva = round_line16(va + size);
|
|
va = trunc_line16(va);
|
|
|
|
while ((eva - va) >= (32 * 16)) {
|
|
cache_r4k_op_32lines_16(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
|
|
va += (32 * 16);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
|
|
va += 16;
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_wb_range_32(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva;
|
|
|
|
eva = round_line32(va + size);
|
|
va = trunc_line32(va);
|
|
|
|
while ((eva - va) >= (32 * 32)) {
|
|
cache_r4k_op_32lines_32(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
|
|
va += (32 * 32);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
|
|
va += 32;
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_wb_range_64(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva;
|
|
|
|
eva = round_line64(va + size);
|
|
va = trunc_line64(va);
|
|
|
|
while ((eva - va) >= (32 * 64)) {
|
|
cache_r4k_op_32lines_64(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
|
|
va += (32 * 64);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
|
|
va += 64;
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
#ifdef CPU_CNMIPS
|
|
|
|
void
|
|
mipsNN_icache_sync_all_128(void)
|
|
{
|
|
SYNCI
|
|
}
|
|
|
|
void
|
|
mipsNN_icache_sync_range_128(vm_offset_t va, vm_size_t size)
|
|
{
|
|
SYNC;
|
|
}
|
|
|
|
void
|
|
mipsNN_icache_sync_range_index_128(vm_offset_t va, vm_size_t size)
|
|
{
|
|
}
|
|
|
|
|
|
void
|
|
mipsNN_pdcache_wbinv_all_128(void)
|
|
{
|
|
}
|
|
|
|
|
|
void
|
|
mipsNN_pdcache_wbinv_range_128(vm_offset_t va, vm_size_t size)
|
|
{
|
|
SYNC;
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_wbinv_range_index_128(vm_offset_t va, vm_size_t size)
|
|
{
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_inv_range_128(vm_offset_t va, vm_size_t size)
|
|
{
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_wb_range_128(vm_offset_t va, vm_size_t size)
|
|
{
|
|
SYNC;
|
|
}
|
|
|
|
#else
|
|
|
|
void
|
|
mipsNN_icache_sync_all_128(void)
|
|
{
|
|
vm_offset_t va, eva;
|
|
|
|
va = MIPS_PHYS_TO_KSEG0(0);
|
|
eva = va + picache_size;
|
|
|
|
/*
|
|
* Since we're hitting the whole thing, we don't have to
|
|
* worry about the N different "ways".
|
|
*/
|
|
|
|
mips_intern_dcache_wbinv_all();
|
|
|
|
while (va < eva) {
|
|
cache_r4k_op_32lines_128(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
|
|
va += (32 * 128);
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
void
|
|
mipsNN_icache_sync_range_128(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva;
|
|
|
|
eva = round_line128(va + size);
|
|
va = trunc_line128(va);
|
|
|
|
mips_intern_dcache_wb_range(va, (eva - va));
|
|
|
|
while ((eva - va) >= (32 * 128)) {
|
|
cache_r4k_op_32lines_128(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
|
|
va += (32 * 128);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
|
|
va += 128;
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
void
|
|
mipsNN_icache_sync_range_index_128(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva, tmpva;
|
|
int i, stride, loopcount;
|
|
|
|
/*
|
|
* Since we're doing Index ops, we expect to not be able
|
|
* to access the address we've been given. So, get the
|
|
* bits that determine the cache index, and make a KSEG0
|
|
* address out of them.
|
|
*/
|
|
va = MIPS_PHYS_TO_KSEG0(va & picache_way_mask);
|
|
|
|
eva = round_line128(va + size);
|
|
va = trunc_line128(va);
|
|
|
|
/*
|
|
* GCC generates better code in the loops if we reference local
|
|
* copies of these global variables.
|
|
*/
|
|
stride = picache_stride;
|
|
loopcount = picache_loopcount;
|
|
|
|
mips_intern_dcache_wbinv_range_index(va, (eva - va));
|
|
|
|
while ((eva - va) >= (32 * 128)) {
|
|
tmpva = va;
|
|
for (i = 0; i < loopcount; i++, tmpva += stride)
|
|
cache_r4k_op_32lines_128(tmpva,
|
|
CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
|
|
va += 32 * 128;
|
|
}
|
|
|
|
while (va < eva) {
|
|
tmpva = va;
|
|
for (i = 0; i < loopcount; i++, tmpva += stride)
|
|
cache_op_r4k_line(tmpva,
|
|
CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
|
|
va += 128;
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_wbinv_all_128(void)
|
|
{
|
|
vm_offset_t va, eva;
|
|
|
|
va = MIPS_PHYS_TO_KSEG0(0);
|
|
eva = va + pdcache_size;
|
|
|
|
/*
|
|
* Since we're hitting the whole thing, we don't have to
|
|
* worry about the N different "ways".
|
|
*/
|
|
|
|
while (va < eva) {
|
|
cache_r4k_op_32lines_128(va,
|
|
CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += (32 * 128);
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
|
|
void
|
|
mipsNN_pdcache_wbinv_range_128(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva;
|
|
|
|
eva = round_line128(va + size);
|
|
va = trunc_line128(va);
|
|
|
|
while ((eva - va) >= (32 * 128)) {
|
|
cache_r4k_op_32lines_128(va,
|
|
CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
|
|
va += (32 * 128);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
|
|
va += 128;
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_wbinv_range_index_128(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva, tmpva;
|
|
int i, stride, loopcount;
|
|
|
|
/*
|
|
* Since we're doing Index ops, we expect to not be able
|
|
* to access the address we've been given. So, get the
|
|
* bits that determine the cache index, and make a KSEG0
|
|
* address out of them.
|
|
*/
|
|
va = MIPS_PHYS_TO_KSEG0(va & pdcache_way_mask);
|
|
|
|
eva = round_line128(va + size);
|
|
va = trunc_line128(va);
|
|
|
|
/*
|
|
* GCC generates better code in the loops if we reference local
|
|
* copies of these global variables.
|
|
*/
|
|
stride = pdcache_stride;
|
|
loopcount = pdcache_loopcount;
|
|
|
|
while ((eva - va) >= (32 * 128)) {
|
|
tmpva = va;
|
|
for (i = 0; i < loopcount; i++, tmpva += stride)
|
|
cache_r4k_op_32lines_128(tmpva,
|
|
CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += 32 * 128;
|
|
}
|
|
|
|
while (va < eva) {
|
|
tmpva = va;
|
|
for (i = 0; i < loopcount; i++, tmpva += stride)
|
|
cache_op_r4k_line(tmpva,
|
|
CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += 128;
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_inv_range_128(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva;
|
|
|
|
eva = round_line128(va + size);
|
|
va = trunc_line128(va);
|
|
|
|
while ((eva - va) >= (32 * 128)) {
|
|
cache_r4k_op_32lines_128(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
|
|
va += (32 * 128);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
|
|
va += 128;
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_wb_range_128(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva;
|
|
|
|
eva = round_line128(va + size);
|
|
va = trunc_line128(va);
|
|
|
|
while ((eva - va) >= (32 * 128)) {
|
|
cache_r4k_op_32lines_128(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
|
|
va += (32 * 128);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
|
|
va += 128;
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
#endif
|
|
|
|
void
|
|
mipsNN_sdcache_wbinv_all_32(void)
|
|
{
|
|
vm_offset_t va = MIPS_PHYS_TO_KSEG0(0);
|
|
vm_offset_t eva = va + sdcache_size;
|
|
|
|
while (va < eva) {
|
|
cache_r4k_op_32lines_32(va,
|
|
CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += (32 * 32);
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_sdcache_wbinv_all_64(void)
|
|
{
|
|
vm_offset_t va = MIPS_PHYS_TO_KSEG0(0);
|
|
vm_offset_t eva = va + sdcache_size;
|
|
|
|
while (va < eva) {
|
|
cache_r4k_op_32lines_64(va,
|
|
CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += (32 * 64);
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_sdcache_wbinv_range_32(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva = round_line32(va + size);
|
|
|
|
va = trunc_line32(va);
|
|
|
|
while ((eva - va) >= (32 * 32)) {
|
|
cache_r4k_op_32lines_32(va,
|
|
CACHE_R4K_SD|CACHEOP_R4K_HIT_WB_INV);
|
|
va += (32 * 32);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB_INV);
|
|
va += 32;
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_sdcache_wbinv_range_64(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva = round_line64(va + size);
|
|
|
|
va = trunc_line64(va);
|
|
|
|
while ((eva - va) >= (32 * 64)) {
|
|
cache_r4k_op_32lines_64(va,
|
|
CACHE_R4K_SD|CACHEOP_R4K_HIT_WB_INV);
|
|
va += (32 * 64);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB_INV);
|
|
va += 64;
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_sdcache_wbinv_range_index_32(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva;
|
|
|
|
/*
|
|
* Since we're doing Index ops, we expect to not be able
|
|
* to access the address we've been given. So, get the
|
|
* bits that determine the cache index, and make a KSEG0
|
|
* address out of them.
|
|
*/
|
|
va = MIPS_PHYS_TO_KSEG0(va & (sdcache_size - 1));
|
|
|
|
eva = round_line32(va + size);
|
|
va = trunc_line32(va);
|
|
|
|
while ((eva - va) >= (32 * 32)) {
|
|
cache_r4k_op_32lines_32(va,
|
|
CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += (32 * 32);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += 32;
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_sdcache_wbinv_range_index_64(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva;
|
|
|
|
/*
|
|
* Since we're doing Index ops, we expect to not be able
|
|
* to access the address we've been given. So, get the
|
|
* bits that determine the cache index, and make a KSEG0
|
|
* address out of them.
|
|
*/
|
|
va = MIPS_PHYS_TO_KSEG0(va & (sdcache_size - 1));
|
|
|
|
eva = round_line64(va + size);
|
|
va = trunc_line64(va);
|
|
|
|
while ((eva - va) >= (32 * 64)) {
|
|
cache_r4k_op_32lines_64(va,
|
|
CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += (32 * 64);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += 64;
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_sdcache_inv_range_32(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva = round_line32(va + size);
|
|
|
|
va = trunc_line32(va);
|
|
|
|
while ((eva - va) >= (32 * 32)) {
|
|
cache_r4k_op_32lines_32(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_INV);
|
|
va += (32 * 32);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_INV);
|
|
va += 32;
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_sdcache_inv_range_64(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva = round_line64(va + size);
|
|
|
|
va = trunc_line64(va);
|
|
|
|
while ((eva - va) >= (32 * 64)) {
|
|
cache_r4k_op_32lines_64(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_INV);
|
|
va += (32 * 64);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_INV);
|
|
va += 64;
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_sdcache_wb_range_32(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva = round_line32(va + size);
|
|
|
|
va = trunc_line32(va);
|
|
|
|
while ((eva - va) >= (32 * 32)) {
|
|
cache_r4k_op_32lines_32(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB);
|
|
va += (32 * 32);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB);
|
|
va += 32;
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_sdcache_wb_range_64(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva = round_line64(va + size);
|
|
|
|
va = trunc_line64(va);
|
|
|
|
while ((eva - va) >= (32 * 64)) {
|
|
cache_r4k_op_32lines_64(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB);
|
|
va += (32 * 64);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB);
|
|
va += 64;
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_sdcache_wbinv_all_128(void)
|
|
{
|
|
vm_offset_t va = MIPS_PHYS_TO_KSEG0(0);
|
|
vm_offset_t eva = va + sdcache_size;
|
|
|
|
while (va < eva) {
|
|
cache_r4k_op_32lines_128(va,
|
|
CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += (32 * 128);
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_sdcache_wbinv_range_128(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva = round_line128(va + size);
|
|
|
|
va = trunc_line128(va);
|
|
|
|
while ((eva - va) >= (32 * 128)) {
|
|
cache_r4k_op_32lines_128(va,
|
|
CACHE_R4K_SD|CACHEOP_R4K_HIT_WB_INV);
|
|
va += (32 * 128);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB_INV);
|
|
va += 128;
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_sdcache_wbinv_range_index_128(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva;
|
|
|
|
/*
|
|
* Since we're doing Index ops, we expect to not be able
|
|
* to access the address we've been given. So, get the
|
|
* bits that determine the cache index, and make a KSEG0
|
|
* address out of them.
|
|
*/
|
|
va = MIPS_PHYS_TO_KSEG0(va & (sdcache_size - 1));
|
|
|
|
eva = round_line128(va + size);
|
|
va = trunc_line128(va);
|
|
|
|
while ((eva - va) >= (32 * 128)) {
|
|
cache_r4k_op_32lines_128(va,
|
|
CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += (32 * 128);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV);
|
|
va += 128;
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_sdcache_inv_range_128(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva = round_line128(va + size);
|
|
|
|
va = trunc_line128(va);
|
|
|
|
while ((eva - va) >= (32 * 128)) {
|
|
cache_r4k_op_32lines_128(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_INV);
|
|
va += (32 * 128);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_INV);
|
|
va += 128;
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_sdcache_wb_range_128(vm_offset_t va, vm_size_t size)
|
|
{
|
|
vm_offset_t eva = round_line128(va + size);
|
|
|
|
va = trunc_line128(va);
|
|
|
|
while ((eva - va) >= (32 * 128)) {
|
|
cache_r4k_op_32lines_128(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB);
|
|
va += (32 * 128);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB);
|
|
va += 128;
|
|
}
|
|
}
|