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451bcf1b36
It is found on boards equipped with LS1028A SoC.
802.1q VLAN grouping is supported.
An external MDIO device is used for communicating with PHYs.
The driver is built as a module by default, it is not included
in GENERIC kernel config.
Submitted by: Lukasz Hajec <lha@semihalf.com>
Kornel Duleba <mindal@semihalf.com>
Obtained from: Semihalf
Sponsored by: Alstom Group
Differential Revision: https://reviews.freebsd.org/D30923
100 lines
4 KiB
C
100 lines
4 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Alstom Group.
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* Copyright (c) 2021 Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _FELIX_REG_H_
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#define _FELIX_REG_H_
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#define BIT(x) (1UL << (x))
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#define FELIX_DEVCPU_GCB_RST 0x70004
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#define FELIX_DEVCPU_GCB_RST_EN BIT(0)
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#define FELIX_ANA_VT 0x287F34
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#define FELIX_ANA_VT_PORTMASK_SHIFT 2
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#define FELIX_ANA_VT_PORTMASK_MASK 0x7F
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#define FELIX_ANA_VT_STS (BIT(0) | BIT(1))
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#define FELIX_ANA_VT_RESET (BIT(0) | BIT(1))
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#define FELIX_ANA_VT_WRITE BIT(1)
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#define FELIX_ANA_VT_READ BIT(0)
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#define FELIX_ANA_VT_IDLE 0
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#define FELIX_ANA_VTIDX 0x287F38
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#define FELIX_ANA_PORT_BASE 0x287800
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#define FELIX_ANA_PORT_OFFSET 0x100
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#define FELIX_ANA_PORT_VLAN_CFG 0x0
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#define FELIX_ANA_PORT_VLAN_CFG_VID_MASK 0xFFF
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#define FELIX_ANA_PORT_VLAN_CFG_POP BIT(18)
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#define FELIX_ANA_PORT_VLAN_CFG_VID_AWARE BIT(20)
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#define FELIX_ANA_PORT_DROP_CFG 0x4
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#define FELIX_ANA_PORT_DROP_CFG_MULTI BIT(0)
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#define FELIX_ANA_PORT_DROP_CFG_NULL BIT(1) /* SRC, or DST MAC == 0 */
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#define FELIX_ANA_PORT_DROP_CFG_CTAGGED_PRIO BIT(2) /* 0x8100, VID == 0 */
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#define FELIX_ANA_PORT_DROP_CFG_STAGGED_PRIO BIT(3) /* 0x88A8, VID == 0 */
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#define FELIX_ANA_PORT_DROP_CFG_CTAGGED BIT(4) /* 0x8100 */
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#define FELIX_ANA_PORT_DROP_CFG_STAGGED BIT(5) /* 0x88A8 */
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#define FELIX_ANA_PORT_DROP_CFG_UNTAGGED BIT(6)
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#define FELIX_ANA_PORT_DROP_CFG_TAGGED \
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(FELIX_ANA_PORT_DROP_CFG_CTAGGED_PRIO | \
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FELIX_ANA_PORT_DROP_CFG_STAGGED_PRIO | \
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FELIX_ANA_PORT_DROP_CFG_CTAGGED | \
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FELIX_ANA_PORT_DROP_CFG_STAGGED)
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#define FELIX_DEVGMII_BASE 0x100000
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#define FELIX_DEVGMII_PORT_OFFSET 0x010000
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#define FELIX_DEVGMII_CLK_CFG 0x0
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#define FELIX_DEVGMII_CLK_CFG_SPEED_1000 1
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#define FELIX_DEVGMII_CLK_CFG_SPEED_100 2
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#define FELIX_DEVGMII_CLK_CFG_SPEED_10 3
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#define FELIX_DEVGMII_MAC_CFG 0x1c
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#define FELIX_DEVGMII_MAC_CFG_TX_ENA BIT(0)
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#define FELIX_DEVGMII_MAC_CFG_RX_ENA BIT(4)
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#define FELIX_DEVGMII_VLAN_CFG 0x28
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#define FELIX_DEVGMII_VLAN_CFG_ENA BIT(0) /* Accept 0x8100 only. */
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#define FELIX_DEVGMII_VLAN_CFG_DOUBLE_ENA BIT(1) /* Inner tag can only be 0x8100. */
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#define FELIX_DEVGMII_VLAN_CFG_LEN_ENA BIT(2) /* Enable VLANMTU. */
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#define FELIX_REW_PORT_BASE 0x030000
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#define FELIX_REW_PORT_OFFSET 0x80
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#define FELIX_REW_PORT_TAG_CFG 0x4
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#define FELIX_REW_PORT_TAG_CFG_MASK (BIT(7) | BIT(8))
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#define FELIX_REW_PORT_TAG_CFG_DIS (0 << 7) /* Port tagging disabled */
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#define FELIX_REW_PORT_TAG_CFG_ALL (2 << 7) /* Tag frames if pvid != 0 */
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#define FELIX_SYS_RAM_CTRL 0x10F24
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#define FELIX_SYS_RAM_CTRL_INIT BIT(1)
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#define FELIX_SYS_CFG 0x10E00
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#define FELIX_SYS_CFG_CORE_EN BIT(0)
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#define FELIX_QSYS_PORT_MODE(port) (0x20F480 + 4*(port))
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#define FELIX_QSYS_PORT_MODE_PORT_ENA BIT(14)
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#endif
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