Andrew Gallatin c5445f8b34 hwpmc : fix AMD perf counter MSR access ... - amd_intr() does not account for the offset (0x200) in the counter MSR address and ends up accessing invalid regions while reading counter value after the 4th counter (0xC001000[8,9,..]) and erroneously updates the counter values for counters [1-4]. - amd_intr() should only check core pmcs for interrupts since other types of pmcs (L3,DF) cannot generate interrupts. - fix pmc NMI's being ignored due to NMI latency on newer AMD processors Note that this fixes a kernel panic due to GPFs accessing MSRs on higher core count AMD cpus (seen on both Rome 7502P, and Threadripper 2990WX 32-core CPUs) Discussed with: markj Submitted by: Shreyank Amartya Differential Revision: https://reviews.freebsd.org/D21553		2019-11-07 19:54:24 +00:00
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hwpmc_amd.c	hwpmc : fix AMD perf counter MSR access	2019-11-07 19:54:24 +00:00
hwpmc_amd.h	hwpmc : fix AMD perf counter MSR access	2019-11-07 19:54:24 +00:00
hwpmc_arm.c
hwpmc_arm64.c	Use a lowercase name for arm64 special registers so they don't conflict	2019-10-30 12:47:00 +00:00
hwpmc_arm64.h
hwpmc_arm64_md.c
hwpmc_armv7.c	Don't refer to the cpu variable in a KASSERT before initializing it.	2019-06-06 15:18:23 +00:00
hwpmc_armv7.h
hwpmc_beri.c	Add support for BERI statcounters.	2019-09-18 16:13:50 +00:00
hwpmc_beri.h	Add support for BERI statcounters.	2019-09-18 16:13:50 +00:00
hwpmc_core.c	hwpmc/core: Adopt to upcoming Skylake TSX errata.	2019-03-12 19:33:25 +00:00
hwpmc_core.h
hwpmc_e500.c
hwpmc_intel.c	hwpmc_intel: List all Silvermont ids.	2019-06-03 16:21:09 +00:00
hwpmc_logging.c
hwpmc_mips.c
hwpmc_mips24k.c
hwpmc_mips74k.c
hwpmc_mod.c	Fix sample check in hwpmc	2019-10-13 22:26:55 +00:00
hwpmc_mpc7xxx.c
hwpmc_octeon.c
hwpmc_powerpc.c
hwpmc_powerpc.h
hwpmc_ppc970.c
hwpmc_riscv.h
hwpmc_soft.c
hwpmc_soft.h
hwpmc_sparc64.c
hwpmc_tsc.c
hwpmc_tsc.h
hwpmc_uncore.c
hwpmc_uncore.h
hwpmc_x86.c
hwpmc_xscale.h
pmc_events.h	Add support for BERI statcounters.	2019-09-18 16:13:50 +00:00