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opnsense-src/sys/riscv
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Ruslan Bukin bf03b1f1f9 Disable interrupts first and then set spinlock_count to 1. 
Otherwise interrupt can be generated just after setting spinlock_count
and before disabling interrupts.

Sponsored by:	DARPA, AFRL
2019-05-07 14:32:17 +00:00
..
conf Configure hz=100 in the QEMU target. 2019-01-03 16:11:21 +00:00
include Provide a template for busdma code for RISC-V. 2019-05-07 13:41:43 +00:00
riscv Disable interrupts first and then set spinlock_count to 1. 2019-05-07 14:32:17 +00:00