Marcel Moolenaar 191bb483f2 Review previous change. It has no relation to the I-cache coherency ... changes and thus unintentional. Spotted by: rdivacky@		2009-10-21 18:44:00 +00:00
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arm	o Introduce vm_sync_icache() for making the I-cache coherent with	2009-10-21 18:38:02 +00:00
at91	- Proprely intialize UART parameters at probe stage, so uart(4)	2009-08-15 15:15:20 +00:00
compile
conf	Sync with other GENERIC kernel configs:	2009-10-13 19:04:01 +00:00
include	Define architectural load bases for PIE binaries. Addresses were selected	2009-10-10 15:31:24 +00:00
mv	Review previous change. It has no relation to the I-cache coherency	2009-10-21 18:44:00 +00:00
sa11x0	Map DPCPU pages into ARM kernel VA space.	2009-07-01 20:07:44 +00:00
xscale	Remove remaining bits of performance counter support.	2009-10-03 13:59:15 +00:00