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0612538e3a
Implement a core clknode driver for the JH7110 (StarFive VisionFive v2) platform. Add clock/reset generator drivers for the PLL, SYS, and AON clock groupings. Co-authored-by: mhorne Reviewed by: mhorne Sponsored by: The FreeBSD Foundation (mhorne's contributions) Differential Revision: https://reviews.freebsd.org/D43037 |
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| .. | ||
| allwinner | ||
| rockchip | ||
| starfive | ||
| xilinx | ||
| clk.c | ||
| clk.h | ||
| clk_bus.c | ||
| clk_div.c | ||
| clk_div.h | ||
| clk_fixed.c | ||
| clk_fixed.h | ||
| clk_gate.c | ||
| clk_gate.h | ||
| clk_link.c | ||
| clk_link.h | ||
| clk_mux.c | ||
| clk_mux.h | ||
| clkdev_if.m | ||
| clknode_if.m | ||