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========================
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LLVM 7.0.0 Release Notes
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========================
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.. contents::
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:local:
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Introduction
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============
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This document contains the release notes for the LLVM Compiler Infrastructure,
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release 7.0.0. Here we describe the status of LLVM, including major improvements
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from the previous release, improvements in various subprojects of LLVM, and
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some of the current users of the code. All LLVM releases may be downloaded
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from the `LLVM releases web site <https://llvm.org/releases/>`_.
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For more information about LLVM, including information about the latest
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release, please check out the `main LLVM web site <https://llvm.org/>`_. If you
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have questions or comments, the `LLVM Developer's Mailing List
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<https://lists.llvm.org/mailman/listinfo/llvm-dev>`_ is a good place to send
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them.
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Non-comprehensive list of changes in this release
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=================================================
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* The Windows installer no longer includes a Visual Studio integration.
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Instead, a new
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`LLVM Compiler Toolchain Visual Studio extension <https://marketplace.visualstudio.com/items?itemName=LLVMExtensions.llvm-toolchain>`_
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is available on the Visual Studio Marketplace. The new integration
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supports Visual Studio 2017.
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* Libraries have been renamed from 7.0 to 7. This change also impacts
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downstream libraries like lldb.
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* The LoopInstSimplify pass (``-loop-instsimplify``) has been removed.
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* Symbols starting with ``?`` are no longer mangled by LLVM when using the
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Windows ``x`` or ``w`` IR mangling schemes.
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* A new tool named :doc:`llvm-exegesis <CommandGuide/llvm-exegesis>` has been
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added. :program:`llvm-exegesis` automatically measures instruction scheduling
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properties (latency/uops) and provides a principled way to edit scheduling
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models.
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* A new tool named :doc:`llvm-mca <CommandGuide/llvm-mca>` has been added.
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:program:`llvm-mca` is a static performance analysis tool that uses
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information available in LLVM to statically predict the performance of
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machine code for a specific CPU.
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* Optimization of floating-point casts is improved. This may cause surprising
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results for code that is relying on the undefined behavior of overflowing
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casts. The optimization can be disabled by specifying a function attribute:
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``"strict-float-cast-overflow"="false"``. This attribute may be created by the
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clang option ``-fno-strict-float-cast-overflow``.
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Code sanitizers can be used to detect affected patterns. The clang option for
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detecting this problem alone is ``-fsanitize=float-cast-overflow``:
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.. code-block:: c
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int main() {
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float x = 4294967296.0f;
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x = (float)((int)x);
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printf("junk in the ftrunc: %f\n", x);
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return 0;
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}
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.. code-block:: bash
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clang -O1 ftrunc.c -fsanitize=float-cast-overflow ; ./a.out
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ftrunc.c:5:15: runtime error: 4.29497e+09 is outside the range of representable values of type 'int'
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junk in the ftrunc: 0.000000
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* ``LLVM_ON_WIN32`` is no longer set by ``llvm/Config/config.h`` and
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``llvm/Config/llvm-config.h``. If you used this macro, use the compiler-set
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``_WIN32`` instead which is set exactly when ``LLVM_ON_WIN32`` used to be set.
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* The ``DEBUG`` macro has been renamed to ``LLVM_DEBUG``, the interface remains
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the same. If you used this macro you need to migrate to the new one.
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You should also clang-format your code to make it easier to integrate future
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changes locally. This can be done with the following bash commands:
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.. code-block:: bash
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git grep -l 'DEBUG' | xargs perl -pi -e 's/\bDEBUG\s?\(/LLVM_DEBUG(/g'
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git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM
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* Early support for UBsan, X-Ray instrumentation and libFuzzer (x86 and x86_64)
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for OpenBSD. Support for MSan (x86_64), X-Ray instrumentation and libFuzzer
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(x86 and x86_64) for FreeBSD.
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* ``SmallVector<T, 0>`` shrank from ``sizeof(void*) * 4 + sizeof(T)`` to
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``sizeof(void*) + sizeof(unsigned) * 2``, smaller than ``std::vector<T>`` on
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64-bit platforms. The maximum capacity is now restricted to ``UINT32_MAX``.
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Since SmallVector doesn't have the exception-safety pessimizations some
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implementations saddle ``std::vector`` with and is better at using ``realloc``,
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it's now a better choice even on the heap (although when ``TinyPtrVector`` works,
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that's even smaller).
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* Preliminary/experimental support for DWARF v5 debugging information,
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including the new ``.debug_names`` accelerator table. DWARF emitted at ``-O0``
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should be fully DWARF v5 compliant. Type units and split DWARF are known
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not to be compliant, and higher optimization levels will still emit some
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information in v4 format.
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* Added support for the ``.rva`` assembler directive for COFF targets.
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* The :program:`llvm-rc` tool (Windows Resource Compiler) has been improved
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a bit. There are still known missing features, but it is generally usable
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in many cases. (The tool still doesn't preprocess input files automatically,
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but it can now handle leftover C declarations in preprocessor output, if
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given output from a preprocessor run externally.)
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* CodeView debug info can now be emitted for MinGW configurations, if requested.
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* The :program:`opt` tool now supports the ``-load-pass-plugin`` option for
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loading pass plugins for the new PassManager.
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* Support for profiling JITed code with perf.
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Changes to the LLVM IR
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----------------------
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* The signatures for the builtins ``@llvm.memcpy``, ``@llvm.memmove``, and
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``@llvm.memset`` have changed. Alignment is no longer an argument, and are
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instead conveyed as parameter attributes.
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* ``invariant.group.barrier`` has been renamed to ``launder.invariant.group``.
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* ``invariant.group`` metadata can now refer only to empty metadata nodes.
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Changes to the AArch64 Target
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-----------------------------
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* The ``.inst`` assembler directive is now usable on both COFF and Mach-O
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targets, in addition to ELF.
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* Support for most remaining COFF relocations has been added.
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* Support for TLS on Windows has been added.
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* Assembler and disassembler support for the ARM Scalable Vector Extension has
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been added.
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Changes to the ARM Target
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-------------------------
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* The ``.inst`` assembler directive is now usable on both COFF and Mach-O
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targets, in addition to ELF. For Thumb, it can now also automatically
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deduce the instruction size, without having to specify it with
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e.g. ``.inst.w`` as before.
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Changes to the Hexagon Target
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-----------------------------
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* Hexagon now supports auto-vectorization for HVX. It is disabled by default
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and can be turned on with ``-fvectorize``. For auto-vectorization to take
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effect, code generation for HVX needs to be enabled with ``-mhvx``.
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The complete set of options should include ``-fvectorize``, ``-mhvx``,
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and ``-mhvx-length={64b|128b}``.
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* The support for Hexagon ISA V4 is deprecated and will be removed in the
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next release.
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Changes to the MIPS Target
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--------------------------
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During this release the MIPS target has:
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* Added support for Virtualization, Global INValidate ASE,
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and CRC ASE instructions.
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* Introduced definitions of ``[d]rem``, ``[d]remu``,
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and microMIPSR6 ``ll/sc`` instructions.
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* Shrink-wrapping is now supported and enabled by default (except for ``-O0``).
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* Extended size reduction pass by the LWP and SWP instructions.
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* Gained initial support of GlobalISel instruction selection framework.
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* Updated the P5600 scheduler model not to use instruction itineraries.
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* Added disassembly support for comparison and fused (negative) multiply
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``add/sub`` instructions.
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* Improved the selection of multiple instructions.
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* Load/store ``lb``, ``sb``, ``ld``, ``sd``, ``lld``, ... instructions
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now support 32/64-bit offsets.
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* Added support for ``y``, ``M``, and ``L`` inline assembler operand codes.
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* Extended list of relocations supported by the ``.reloc`` directive
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* Fixed using a wrong register class for creating an emergency
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spill slot for mips3 / n64 ABI.
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* MIPS relocation types were generated for microMIPS code.
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* Corrected definitions of multiple instructions (``lwp``, ``swp``, ``ctc2``,
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``cfc2``, ``sync``, ``synci``, ``cvt.d.w``, ...).
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* Fixed atomic operations at ``-O0`` level.
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* Fixed local dynamic TLS with Sym64
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Changes to the PowerPC Target
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-----------------------------
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During this release the PowerPC target has:
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* Replaced the list scheduler for post register allocation with the machine scheduler.
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* Added support for ``coldcc`` calling convention.
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* Added support for ``symbol@high`` and ``symbol@higha`` symbol modifiers.
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* Added support for quad-precision floating point type (``__float128``) under the llvm option ``-enable-ppc-quad-precision``.
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* Added dump function to ``LatencyPriorityQueue``.
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* Completed the Power9 scheduler model.
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* Optimized TLS code generation.
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* Improved MachineLICM for hoisting constant stores.
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* Improved code generation to reduce register use by using more register + immediate instructions.
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* Improved code generation to better exploit rotate-and-mask instructions.
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* Fixed the bug in dynamic loader for JIT which crashed NNVM.
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* Numerous bug fixes and code cleanups.
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Changes to the SystemZ Target
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-----------------------------
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During this release the SystemZ target has:
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* Added support for vector registers in inline asm statements.
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* Added support for stackmaps, patchpoints, and the anyregcc
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calling convention.
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* Changed the default function alignment to 16 bytes.
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* Improved codegen for condition code handling.
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* Improved instruction scheduling and microarchitecture tuning for z13/z14.
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* Fixed support for generating GCOV coverage data.
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* Fixed some codegen bugs.
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Changes to the X86 Target
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-------------------------
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* The calling convention for the ``f80`` data type on MinGW targets has been
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fixed. Normally, the calling convention for this type is handled within clang,
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but if an intrinsic is used, which LLVM expands into a libcall, the
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proper calling convention needs to be supported in LLVM as well. (Note,
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on Windows, this data type is only used for long doubles in MinGW
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environments - in MSVC environments, long doubles are the same size as
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normal doubles.)
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Changes to the OCaml bindings
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-----------------------------
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* Removed ``add_bb_vectorize``.
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Changes to the C API
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--------------------
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* Removed ``LLVMAddBBVectorizePass``. The implementation was removed and the C
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interface was made a deprecated no-op in LLVM 5. Use
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``LLVMAddSLPVectorizePass`` instead to get the supported SLP vectorizer.
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* Expanded the OrcJIT APIs so they can register event listeners like debuggers
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and profilers.
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Changes to the DAG infrastructure
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---------------------------------
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* ``ADDC``/``ADDE``/``SUBC``/``SUBE`` are now deprecated and will default to expand. Backends
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that wish to continue to use these opcodes should explicitely request to do so
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using ``setOperationAction`` in their ``TargetLowering``. New backends
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should use ``UADDO``/``ADDCARRY``/``USUBO``/``SUBCARRY`` instead of the deprecated opcodes.
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* The ``SETCCE`` opcode has now been removed in favor of ``SETCCCARRY``.
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* TableGen now supports multi-alternative pattern fragments via the ``PatFrags``
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class. ``PatFrag`` is now derived from ``PatFrags``, which may require minor
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changes to backends that directly access ``PatFrag`` members.
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External Open Source Projects Using LLVM 7
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==========================================
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Zig Programming Language
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------------------------
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`Zig <https://ziglang.org>`_ is an open-source programming language designed
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for robustness, optimality, and clarity. Zig is an alternative to C, providing
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high level features such as generics, compile time function execution, partial
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evaluation, and LLVM-based coroutines, while exposing low level LLVM IR
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features such as aliases and intrinsics. Zig uses Clang to provide automatic
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import of .h symbols - even inline functions and macros. Zig uses LLD combined
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with lazily building compiler-rt to provide out-of-the-box cross-compiling for
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all supported targets.
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Additional Information
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======================
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A wide variety of additional information is available on the `LLVM web page
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<https://llvm.org/>`_, in particular in the `documentation
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<https://llvm.org/docs/>`_ section. The web page also contains versions of the
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API documentation which is up-to-date with the Subversion version of the source
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code. You can access versions of these documents specific to this release by
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going into the ``llvm/docs/`` directory in the LLVM tree.
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If you have any questions or comments about LLVM, please feel free to contact
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us via the `mailing lists <https://llvm.org/docs/#mailing-lists>`_.
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