Oleksandr Tymoshenko 8e01fdea2b Add sysctls to control PS-PL level shifters and FCLK settings. ... PL (programmable logic) uses FCLK0..FCLK3 as a clock sources. Normally they're configured by first stage boot loader (FSBL) and normal user never has to touch them. These sysctls may come useful for hardware developers hw.fpga.fclk.N.source: clock source (IO, DDR, ARM) hw.fpga.fclk.N.freq: requested frequency in Hz hw.fpga.fclk.N.actual_freq: actual frequency in Hz (R/O) hw.fgpa.level_shifters: 0/1 to enable/disable PS-PL level shifters, normally they're enabled either by FSBL or after programming FPGA through devcfg(4)		2015-03-05 21:41:58 +00:00
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zedboard
files.zynq7	Rename bus_space-v6.c to bus_space_base.c, because it's not v6-specific	2015-01-21 03:44:29 +00:00
std.zynq7	Remove -Wa,-march=armv7a from arm kernel configs, it makes clang 3.5 sad	2015-01-01 23:21:46 +00:00
uart_dev_cdnc.c	opt_global.h is included automatically in the build. No need to	2014-11-18 17:06:56 +00:00
zy7_devcfg.c	Add sysctls to control PS-PL level shifters and FCLK settings.	2015-03-05 21:41:58 +00:00
zy7_ehci.c	Add 64-bit DMA support in the XHCI controller driver.	2015-01-05 20:22:18 +00:00
zy7_gpio.c	Implement GPIO_GET_BUS() method for all GPIO drivers.	2015-01-31 19:32:14 +00:00
zy7_l2cache.c
zy7_machdep.c	opt_global.h is included automatically in the build. No need to	2014-11-18 17:06:56 +00:00
zy7_mp.c	Enable the snoop control unit during MP startup, rather than relying on	2015-01-16 19:49:10 +00:00
zy7_reg.h	Convert the Zynq SoC support to the new routines for static device mapping.	2014-04-30 14:38:13 +00:00
zy7_slcr.c	Add sysctls to control PS-PL level shifters and FCLK settings.	2015-03-05 21:41:58 +00:00
zy7_slcr.h	Add sysctls to control PS-PL level shifters and FCLK settings.	2015-03-05 21:41:58 +00:00