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Changes since 1.26.6.0 are listed here. This list comes from the Release Notes for "Chelsio Unified Wire 3.17.0.0 for Linux" dated 2022-07-29. Fixes ----- BASE: - Enabled all MA parity interrupt bits. - Use config file value to override number of rx channel. nrxch=1 was not handled in the firmware. - Replaced read only registers with new registers EDC_H_BIST_USER_WDATA0, EDC_H_BIST_USER_WDATA1 and EDC_H_BIST_CMD_LEN to dump the uP memory parity error status registers. - 10G simplex module support enabled. Obtained from: Chelsio Communications MFC after: 1 month Sponsored by: Chelsio Communications |
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| .. | ||
| ccr | ||
| cxgbei | ||
| if_cc | ||
| if_ccv | ||
| if_cxgbe | ||
| if_cxgbev | ||
| if_cxl | ||
| if_cxlv | ||
| iw_cxgbe | ||
| t4_firmware | ||
| t5_firmware | ||
| t6_firmware | ||
| tom | ||
| Makefile | ||