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cdcd52d41e
This is an initial commit for RDMA FreeBSD driver for Intel(R) Ethernet Controller E810, called irdma. Supporting both RoCEv2 and iWARP protocols in per-PF manner, RoCEv2 being the default. Testing has been done using krping tool, perftest, ucmatose, rping, ud_pingpong, rc_pingpong and others. Signed-off-by: Eric Joyner <erj@FreeBSD.org> Reviewed by: #manpages (pauamma_gundo.com) [documentation] MFC after: 1 week Relnotes: yes Sponsored by: Intel Corporation Differential Revision: https://reviews.freebsd.org/D34690
318 lines
9.8 KiB
C
318 lines
9.8 KiB
C
/*-
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* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
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*
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* Copyright (c) 2016 - 2021 Intel Corporation
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenFabrics.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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/*$FreeBSD$*/
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#include "osdep.h"
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#include "irdma_hmc.h"
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#include "irdma_defs.h"
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#include "irdma_type.h"
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#include "irdma_protos.h"
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#include "irdma_uda.h"
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#include "irdma_uda_d.h"
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/**
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* irdma_sc_access_ah() - Create, modify or delete AH
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* @cqp: struct for cqp hw
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* @info: ah information
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* @op: Operation
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* @scratch: u64 saved to be used during cqp completion
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*/
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int
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irdma_sc_access_ah(struct irdma_sc_cqp *cqp, struct irdma_ah_info *info,
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u32 op, u64 scratch)
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{
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__le64 *wqe;
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u64 qw1, qw2;
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wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
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if (!wqe)
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return -ENOSPC;
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set_64bit_val(wqe, IRDMA_BYTE_0, LS_64_1(info->mac_addr[5], 16) |
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LS_64_1(info->mac_addr[4], 24) |
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LS_64_1(info->mac_addr[3], 32) |
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LS_64_1(info->mac_addr[2], 40) |
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LS_64_1(info->mac_addr[1], 48) |
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LS_64_1(info->mac_addr[0], 56));
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qw1 = LS_64(info->pd_idx, IRDMA_UDA_CQPSQ_MAV_PDINDEXLO) |
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LS_64(info->tc_tos, IRDMA_UDA_CQPSQ_MAV_TC) |
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LS_64(info->vlan_tag, IRDMA_UDAQPC_VLANTAG);
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qw2 = LS_64(info->dst_arpindex, IRDMA_UDA_CQPSQ_MAV_ARPINDEX) |
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LS_64(info->flow_label, IRDMA_UDA_CQPSQ_MAV_FLOWLABEL) |
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LS_64(info->hop_ttl, IRDMA_UDA_CQPSQ_MAV_HOPLIMIT) |
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LS_64(info->pd_idx >> 16, IRDMA_UDA_CQPSQ_MAV_PDINDEXHI);
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if (!info->ipv4_valid) {
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set_64bit_val(wqe, IRDMA_BYTE_40,
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LS_64(info->dest_ip_addr[0], IRDMA_UDA_CQPSQ_MAV_ADDR0) |
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LS_64(info->dest_ip_addr[1], IRDMA_UDA_CQPSQ_MAV_ADDR1));
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set_64bit_val(wqe, IRDMA_BYTE_32,
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LS_64(info->dest_ip_addr[2], IRDMA_UDA_CQPSQ_MAV_ADDR2) |
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LS_64(info->dest_ip_addr[3], IRDMA_UDA_CQPSQ_MAV_ADDR3));
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set_64bit_val(wqe, IRDMA_BYTE_56,
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LS_64(info->src_ip_addr[0], IRDMA_UDA_CQPSQ_MAV_ADDR0) |
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LS_64(info->src_ip_addr[1], IRDMA_UDA_CQPSQ_MAV_ADDR1));
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set_64bit_val(wqe, IRDMA_BYTE_48,
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LS_64(info->src_ip_addr[2], IRDMA_UDA_CQPSQ_MAV_ADDR2) |
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LS_64(info->src_ip_addr[3], IRDMA_UDA_CQPSQ_MAV_ADDR3));
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} else {
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set_64bit_val(wqe, IRDMA_BYTE_32,
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LS_64(info->dest_ip_addr[0], IRDMA_UDA_CQPSQ_MAV_ADDR3));
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set_64bit_val(wqe, IRDMA_BYTE_48,
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LS_64(info->src_ip_addr[0], IRDMA_UDA_CQPSQ_MAV_ADDR3));
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}
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set_64bit_val(wqe, IRDMA_BYTE_8, qw1);
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set_64bit_val(wqe, IRDMA_BYTE_16, qw2);
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irdma_wmb(); /* need write block before writing WQE header */
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set_64bit_val(
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wqe, IRDMA_BYTE_24,
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LS_64(cqp->polarity, IRDMA_UDA_CQPSQ_MAV_WQEVALID) |
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LS_64(op, IRDMA_UDA_CQPSQ_MAV_OPCODE) |
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LS_64(info->do_lpbk, IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK) |
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LS_64(info->ipv4_valid, IRDMA_UDA_CQPSQ_MAV_IPV4VALID) |
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LS_64(info->ah_idx, IRDMA_UDA_CQPSQ_MAV_AVIDX) |
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LS_64(info->insert_vlan_tag,
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IRDMA_UDA_CQPSQ_MAV_INSERTVLANTAG));
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irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "MANAGE_AH WQE", wqe,
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IRDMA_CQP_WQE_SIZE * 8);
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irdma_sc_cqp_post_sq(cqp);
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return 0;
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}
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/**
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* irdma_create_mg_ctx() - create a mcg context
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* @info: multicast group context info
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*/
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static int
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irdma_create_mg_ctx(struct irdma_mcast_grp_info *info)
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{
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struct irdma_mcast_grp_ctx_entry_info *entry_info = NULL;
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u8 idx = 0; /* index in the array */
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u8 ctx_idx = 0; /* index in the MG context */
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memset(info->dma_mem_mc.va, 0, IRDMA_MAX_MGS_PER_CTX * sizeof(u64));
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for (idx = 0; idx < IRDMA_MAX_MGS_PER_CTX; idx++) {
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entry_info = &info->mg_ctx_info[idx];
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if (entry_info->valid_entry) {
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set_64bit_val((__le64 *) info->dma_mem_mc.va,
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ctx_idx * sizeof(u64),
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LS_64(entry_info->dest_port, IRDMA_UDA_MGCTX_DESTPORT) |
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LS_64(entry_info->valid_entry, IRDMA_UDA_MGCTX_VALIDENT) |
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LS_64(entry_info->qp_id, IRDMA_UDA_MGCTX_QPID));
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ctx_idx++;
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}
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}
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return 0;
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}
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/**
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* irdma_access_mcast_grp() - Access mcast group based on op
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* @cqp: Control QP
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* @info: multicast group context info
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* @op: operation to perform
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* @scratch: u64 saved to be used during cqp completion
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*/
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int
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irdma_access_mcast_grp(struct irdma_sc_cqp *cqp,
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struct irdma_mcast_grp_info *info, u32 op,
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u64 scratch)
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{
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__le64 *wqe;
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int ret_code = 0;
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if (info->mg_id >= IRDMA_UDA_MAX_FSI_MGS) {
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irdma_debug(cqp->dev, IRDMA_DEBUG_WQE, "mg_id out of range\n");
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return -EINVAL;
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}
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wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
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if (!wqe) {
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irdma_debug(cqp->dev, IRDMA_DEBUG_WQE, "ring full\n");
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return -ENOSPC;
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}
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ret_code = irdma_create_mg_ctx(info);
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if (ret_code)
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return ret_code;
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set_64bit_val(wqe, IRDMA_BYTE_32, info->dma_mem_mc.pa);
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set_64bit_val(wqe, IRDMA_BYTE_16,
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LS_64(info->vlan_id, IRDMA_UDA_CQPSQ_MG_VLANID) |
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LS_64(info->qs_handle, IRDMA_UDA_CQPSQ_QS_HANDLE));
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set_64bit_val(wqe, IRDMA_BYTE_0, LS_64_1(info->dest_mac_addr[5], 0) |
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LS_64_1(info->dest_mac_addr[4], 8) |
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LS_64_1(info->dest_mac_addr[3], 16) |
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LS_64_1(info->dest_mac_addr[2], 24) |
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LS_64_1(info->dest_mac_addr[1], 32) |
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LS_64_1(info->dest_mac_addr[0], 40));
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set_64bit_val(wqe, IRDMA_BYTE_8,
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LS_64(info->hmc_fcn_id, IRDMA_UDA_CQPSQ_MG_HMC_FCN_ID));
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if (!info->ipv4_valid) {
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set_64bit_val(wqe, IRDMA_BYTE_56,
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LS_64(info->dest_ip_addr[0], IRDMA_UDA_CQPSQ_MAV_ADDR0) |
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LS_64(info->dest_ip_addr[1], IRDMA_UDA_CQPSQ_MAV_ADDR1));
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set_64bit_val(wqe, IRDMA_BYTE_48,
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LS_64(info->dest_ip_addr[2], IRDMA_UDA_CQPSQ_MAV_ADDR2) |
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LS_64(info->dest_ip_addr[3], IRDMA_UDA_CQPSQ_MAV_ADDR3));
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} else {
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set_64bit_val(wqe, IRDMA_BYTE_48,
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LS_64(info->dest_ip_addr[0], IRDMA_UDA_CQPSQ_MAV_ADDR3));
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}
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irdma_wmb(); /* need write memory block before writing the WQE header. */
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set_64bit_val(wqe, IRDMA_BYTE_24,
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LS_64(cqp->polarity, IRDMA_UDA_CQPSQ_MG_WQEVALID) |
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LS_64(op, IRDMA_UDA_CQPSQ_MG_OPCODE) |
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LS_64(info->mg_id, IRDMA_UDA_CQPSQ_MG_MGIDX) |
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LS_64(info->vlan_valid, IRDMA_UDA_CQPSQ_MG_VLANVALID) |
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LS_64(info->ipv4_valid, IRDMA_UDA_CQPSQ_MG_IPV4VALID));
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irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "MANAGE_MCG WQE", wqe,
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IRDMA_CQP_WQE_SIZE * 8);
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irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "MCG_HOST CTX WQE",
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info->dma_mem_mc.va, IRDMA_MAX_MGS_PER_CTX * 8);
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irdma_sc_cqp_post_sq(cqp);
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return 0;
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}
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/**
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* irdma_compare_mgs - Compares two multicast group structures
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* @entry1: Multcast group info
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* @entry2: Multcast group info in context
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*/
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static bool
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irdma_compare_mgs(struct irdma_mcast_grp_ctx_entry_info *entry1,
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struct irdma_mcast_grp_ctx_entry_info *entry2)
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{
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if (entry1->dest_port == entry2->dest_port &&
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entry1->qp_id == entry2->qp_id)
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return true;
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return false;
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}
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/**
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* irdma_sc_add_mcast_grp - Allocates mcast group entry in ctx
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* @ctx: Multcast group context
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* @mg: Multcast group info
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*/
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int
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irdma_sc_add_mcast_grp(struct irdma_mcast_grp_info *ctx,
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struct irdma_mcast_grp_ctx_entry_info *mg)
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{
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u32 idx;
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bool free_entry_found = false;
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u32 free_entry_idx = 0;
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/* find either an identical or a free entry for a multicast group */
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for (idx = 0; idx < IRDMA_MAX_MGS_PER_CTX; idx++) {
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if (ctx->mg_ctx_info[idx].valid_entry) {
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if (irdma_compare_mgs(&ctx->mg_ctx_info[idx], mg)) {
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ctx->mg_ctx_info[idx].use_cnt++;
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return 0;
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}
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continue;
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}
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if (!free_entry_found) {
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free_entry_found = true;
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free_entry_idx = idx;
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}
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}
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if (free_entry_found) {
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ctx->mg_ctx_info[free_entry_idx] = *mg;
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ctx->mg_ctx_info[free_entry_idx].valid_entry = true;
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ctx->mg_ctx_info[free_entry_idx].use_cnt = 1;
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ctx->no_of_mgs++;
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return 0;
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}
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return -ENOMEM;
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}
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/**
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* irdma_sc_del_mcast_grp - Delete mcast group
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* @ctx: Multcast group context
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* @mg: Multcast group info
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*
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* Finds and removes a specific mulicast group from context, all
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* parameters must match to remove a multicast group.
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*/
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int
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irdma_sc_del_mcast_grp(struct irdma_mcast_grp_info *ctx,
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struct irdma_mcast_grp_ctx_entry_info *mg)
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{
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u32 idx;
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/* find an entry in multicast group context */
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for (idx = 0; idx < IRDMA_MAX_MGS_PER_CTX; idx++) {
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if (!ctx->mg_ctx_info[idx].valid_entry)
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continue;
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if (irdma_compare_mgs(mg, &ctx->mg_ctx_info[idx])) {
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ctx->mg_ctx_info[idx].use_cnt--;
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if (!ctx->mg_ctx_info[idx].use_cnt) {
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ctx->mg_ctx_info[idx].valid_entry = false;
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ctx->no_of_mgs--;
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/* Remove gap if element was not the last */
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if (idx != ctx->no_of_mgs &&
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ctx->no_of_mgs > 0) {
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irdma_memcpy(&ctx->mg_ctx_info[idx],
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&ctx->mg_ctx_info[ctx->no_of_mgs - 1],
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sizeof(ctx->mg_ctx_info[idx]));
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ctx->mg_ctx_info[ctx->no_of_mgs - 1].valid_entry = false;
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}
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}
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return 0;
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}
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}
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return -EINVAL;
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}
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