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cdcd52d41e
This is an initial commit for RDMA FreeBSD driver for Intel(R) Ethernet Controller E810, called irdma. Supporting both RoCEv2 and iWARP protocols in per-PF manner, RoCEv2 being the default. Testing has been done using krping tool, perftest, ucmatose, rping, ud_pingpong, rc_pingpong and others. Signed-off-by: Eric Joyner <erj@FreeBSD.org> Reviewed by: #manpages (pauamma_gundo.com) [documentation] MFC after: 1 week Relnotes: yes Sponsored by: Intel Corporation Differential Revision: https://reviews.freebsd.org/D34690
418 lines
13 KiB
C
418 lines
13 KiB
C
/*-
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* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
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*
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* Copyright (c) 2017 - 2021 Intel Corporation
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenFabrics.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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/*$FreeBSD$*/
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#include "osdep.h"
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#include "irdma_type.h"
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#include "icrdma_hw.h"
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void disable_prefetch(struct irdma_hw *hw);
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void disable_tx_spad(struct irdma_hw *hw);
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void rdpu_ackreqpmthresh(struct irdma_hw *hw);
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static u32 icrdma_regs[IRDMA_MAX_REGS] = {
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PFPE_CQPTAIL,
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PFPE_CQPDB,
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PFPE_CCQPSTATUS,
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PFPE_CCQPHIGH,
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PFPE_CCQPLOW,
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PFPE_CQARM,
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PFPE_CQACK,
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PFPE_AEQALLOC,
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PFPE_CQPERRCODES,
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PFPE_WQEALLOC,
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GLINT_DYN_CTL(0),
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ICRDMA_DB_ADDR_OFFSET,
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GLPCI_LBARCTRL,
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GLPE_CPUSTATUS0,
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GLPE_CPUSTATUS1,
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GLPE_CPUSTATUS2,
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PFINT_AEQCTL,
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GLINT_CEQCTL(0),
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VSIQF_PE_CTL1(0),
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PFHMC_PDINV,
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GLHMC_VFPDINV(0),
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GLPE_CRITERR,
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GLINT_RATE(0),
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};
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static u64 icrdma_masks[IRDMA_MAX_MASKS] = {
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ICRDMA_CCQPSTATUS_CCQP_DONE_M,
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ICRDMA_CCQPSTATUS_CCQP_ERR_M,
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ICRDMA_CQPSQ_STAG_PDID_M,
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ICRDMA_CQPSQ_CQ_CEQID_M,
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ICRDMA_CQPSQ_CQ_CQID_M,
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ICRDMA_COMMIT_FPM_CQCNT_M,
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};
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static u64 icrdma_shifts[IRDMA_MAX_SHIFTS] = {
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ICRDMA_CCQPSTATUS_CCQP_DONE_S,
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ICRDMA_CCQPSTATUS_CCQP_ERR_S,
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ICRDMA_CQPSQ_STAG_PDID_S,
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ICRDMA_CQPSQ_CQ_CEQID_S,
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ICRDMA_CQPSQ_CQ_CQID_S,
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ICRDMA_COMMIT_FPM_CQCNT_S,
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};
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/**
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* icrdma_ena_irq - Enable interrupt
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* @dev: pointer to the device structure
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* @idx: vector index
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*/
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static void
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icrdma_ena_irq(struct irdma_sc_dev *dev, u32 idx)
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{
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u32 val;
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u32 interval = 0;
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if (dev->ceq_itr && dev->aeq->msix_idx != idx)
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interval = dev->ceq_itr >> 1; /* 2 usec units */
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val = LS_64(0, IRDMA_GLINT_DYN_CTL_ITR_INDX) |
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LS_64(interval, IRDMA_GLINT_DYN_CTL_INTERVAL) |
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IRDMA_GLINT_DYN_CTL_INTENA_M | IRDMA_GLINT_DYN_CTL_CLEARPBA_M;
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writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx);
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}
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/**
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* icrdma_disable_irq - Disable interrupt
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* @dev: pointer to the device structure
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* @idx: vector index
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*/
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static void
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icrdma_disable_irq(struct irdma_sc_dev *dev, u32 idx)
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{
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writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx);
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}
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/**
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* icrdma_cfg_ceq- Configure CEQ interrupt
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* @dev: pointer to the device structure
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* @ceq_id: Completion Event Queue ID
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* @idx: vector index
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* @enable: True to enable, False disables
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*/
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static void
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icrdma_cfg_ceq(struct irdma_sc_dev *dev, u32 ceq_id, u32 idx,
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bool enable)
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{
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u32 reg_val;
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reg_val = enable ? IRDMA_GLINT_CEQCTL_CAUSE_ENA_M : 0;
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reg_val |= (idx << IRDMA_GLINT_CEQCTL_MSIX_INDX_S) |
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IRDMA_GLINT_CEQCTL_ITR_INDX_M;
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writel(reg_val, dev->hw_regs[IRDMA_GLINT_CEQCTL] + ceq_id);
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}
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static const struct irdma_irq_ops icrdma_irq_ops = {
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.irdma_cfg_aeq = irdma_cfg_aeq,
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.irdma_cfg_ceq = icrdma_cfg_ceq,
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.irdma_dis_irq = icrdma_disable_irq,
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.irdma_en_irq = icrdma_ena_irq,
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};
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static const struct irdma_hw_stat_map icrdma_hw_stat_map[] = {
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[IRDMA_HW_STAT_INDEX_RXVLANERR] = {0, 32, IRDMA_MAX_STATS_24},
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[IRDMA_HW_STAT_INDEX_IP4RXOCTS] = {8, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP4RXPKTS] = {16, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP4RXDISCARD] = {24, 32, IRDMA_MAX_STATS_32},
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[IRDMA_HW_STAT_INDEX_IP4RXTRUNC] = {24, 0, IRDMA_MAX_STATS_32},
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[IRDMA_HW_STAT_INDEX_IP4RXFRAGS] = {32, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP4RXMCOCTS] = {40, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP4RXMCPKTS] = {48, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP6RXOCTS] = {56, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP6RXPKTS] = {64, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP6RXDISCARD] = {72, 32, IRDMA_MAX_STATS_32},
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[IRDMA_HW_STAT_INDEX_IP6RXTRUNC] = {72, 0, IRDMA_MAX_STATS_32},
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[IRDMA_HW_STAT_INDEX_IP6RXFRAGS] = {80, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP6RXMCOCTS] = {88, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP6RXMCPKTS] = {96, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP4TXOCTS] = {104, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP4TXPKTS] = {112, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP4TXFRAGS] = {120, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP4TXMCOCTS] = {128, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP4TXMCPKTS] = {136, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP6TXOCTS] = {144, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP6TXPKTS] = {152, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP6TXFRAGS] = {160, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP6TXMCOCTS] = {168, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP6TXMCPKTS] = {176, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_IP4TXNOROUTE] = {184, 32, IRDMA_MAX_STATS_24},
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[IRDMA_HW_STAT_INDEX_IP6TXNOROUTE] = {184, 0, IRDMA_MAX_STATS_24},
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[IRDMA_HW_STAT_INDEX_TCPRXSEGS] = {192, 32, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_TCPRXOPTERR] = {200, 32, IRDMA_MAX_STATS_24},
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[IRDMA_HW_STAT_INDEX_TCPRXPROTOERR] = {200, 0, IRDMA_MAX_STATS_24},
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[IRDMA_HW_STAT_INDEX_TCPTXSEG] = {208, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_TCPRTXSEG] = {216, 32, IRDMA_MAX_STATS_32},
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[IRDMA_HW_STAT_INDEX_UDPRXPKTS] = {224, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_UDPTXPKTS] = {232, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_RDMARXWRS] = {240, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_RDMARXRDS] = {248, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_RDMARXSNDS] = {256, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_RDMATXWRS] = {264, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_RDMATXRDS] = {272, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_RDMATXSNDS] = {280, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_RDMAVBND] = {288, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_RDMAVINV] = {296, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_RXNPECNMARKEDPKTS] = {304, 0, IRDMA_MAX_STATS_48},
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[IRDMA_HW_STAT_INDEX_RXRPCNPIGNORED] = {312, 32, IRDMA_MAX_STATS_16},
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[IRDMA_HW_STAT_INDEX_RXRPCNPHANDLED] = {312, 0, IRDMA_MAX_STATS_32},
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[IRDMA_HW_STAT_INDEX_TXNPCNPSENT] = {320, 0, IRDMA_MAX_STATS_32},
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};
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void
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icrdma_init_hw(struct irdma_sc_dev *dev)
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{
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int i;
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u8 IOMEM *hw_addr;
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for (i = 0; i < IRDMA_MAX_REGS; ++i) {
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hw_addr = dev->hw->hw_addr;
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if (i == IRDMA_DB_ADDR_OFFSET)
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hw_addr = NULL;
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dev->hw_regs[i] = (u32 IOMEM *) (hw_addr + icrdma_regs[i]);
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}
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dev->hw_attrs.max_hw_vf_fpm_id = IRDMA_MAX_VF_FPM_ID;
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dev->hw_attrs.first_hw_vf_fpm_id = IRDMA_FIRST_VF_FPM_ID;
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for (i = 0; i < IRDMA_MAX_SHIFTS; ++i)
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dev->hw_shifts[i] = icrdma_shifts[i];
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for (i = 0; i < IRDMA_MAX_MASKS; ++i)
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dev->hw_masks[i] = icrdma_masks[i];
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dev->wqe_alloc_db = dev->hw_regs[IRDMA_WQEALLOC];
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dev->cq_arm_db = dev->hw_regs[IRDMA_CQARM];
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dev->aeq_alloc_db = dev->hw_regs[IRDMA_AEQALLOC];
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dev->cqp_db = dev->hw_regs[IRDMA_CQPDB];
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dev->cq_ack_db = dev->hw_regs[IRDMA_CQACK];
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dev->irq_ops = &icrdma_irq_ops;
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dev->hw_stats_map = icrdma_hw_stat_map;
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dev->hw_attrs.max_hw_ird = ICRDMA_MAX_IRD_SIZE;
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dev->hw_attrs.max_hw_ord = ICRDMA_MAX_ORD_SIZE;
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dev->hw_attrs.max_stat_inst = ICRDMA_MAX_STATS_COUNT;
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dev->hw_attrs.max_stat_idx = IRDMA_HW_STAT_INDEX_MAX_GEN_2;
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dev->hw_attrs.uk_attrs.max_hw_wq_frags = ICRDMA_MAX_WQ_FRAGMENT_COUNT;
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dev->hw_attrs.uk_attrs.max_hw_read_sges = ICRDMA_MAX_SGE_RD;
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dev->hw_attrs.uk_attrs.max_hw_wq_size = IRDMA_QP_WQE_MAX_SIZE;
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dev->hw_attrs.uk_attrs.min_sw_wq_size = IRDMA_QP_SW_MIN_WQSIZE;
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dev->hw_attrs.uk_attrs.max_hw_sq_chunk = IRDMA_MAX_QUANTA_PER_WR;
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disable_tx_spad(dev->hw);
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disable_prefetch(dev->hw);
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rdpu_ackreqpmthresh(dev->hw);
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dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_RELAX_RQ_ORDER;
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dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_RTS_AE |
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IRDMA_FEATURE_CQ_RESIZE;
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}
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void
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irdma_init_config_check(struct irdma_config_check *cc, u8 traffic_class, u16 qs_handle)
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{
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cc->config_ok = false;
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cc->traffic_class = traffic_class;
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cc->qs_handle = qs_handle;
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cc->lfc_set = 0;
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cc->pfc_set = 0;
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}
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static bool
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irdma_is_lfc_set(struct irdma_config_check *cc, struct irdma_sc_vsi *vsi)
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{
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u32 lfc = 1;
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u8 fn_id = vsi->dev->hmc_fn_id;
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lfc &= (rd32(vsi->dev->hw,
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PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_0 + 4 * fn_id) >> 8);
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lfc &= (rd32(vsi->dev->hw,
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PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_0 + 4 * fn_id) >> 8);
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lfc &= rd32(vsi->dev->hw,
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PRTMAC_HSEC_CTL_RX_ENABLE_GPP_0 + 4 * vsi->dev->hmc_fn_id);
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if (lfc)
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return true;
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return false;
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}
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static bool
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irdma_check_tc_has_pfc(struct irdma_sc_vsi *vsi, u64 reg_offset, u16 traffic_class)
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{
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u32 value, pfc = 0;
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u32 i;
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value = rd32(vsi->dev->hw, reg_offset);
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for (i = 0; i < 4; i++)
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pfc |= (value >> (8 * i + traffic_class)) & 0x1;
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if (pfc)
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return true;
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return false;
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}
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static bool
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irdma_is_pfc_set(struct irdma_config_check *cc, struct irdma_sc_vsi *vsi)
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{
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u32 pause;
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u8 fn_id = vsi->dev->hmc_fn_id;
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pause = (rd32(vsi->dev->hw,
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PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_0 + 4 * fn_id) >>
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cc->traffic_class) & BIT(0);
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pause &= (rd32(vsi->dev->hw,
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PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_0 + 4 * fn_id) >>
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cc->traffic_class) & BIT(0);
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return irdma_check_tc_has_pfc(vsi, GLDCB_TC2PFC, cc->traffic_class) &&
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pause;
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}
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bool
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irdma_is_config_ok(struct irdma_config_check *cc, struct irdma_sc_vsi *vsi)
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{
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cc->lfc_set = irdma_is_lfc_set(cc, vsi);
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cc->pfc_set = irdma_is_pfc_set(cc, vsi);
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cc->config_ok = cc->lfc_set || cc->pfc_set;
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return cc->config_ok;
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}
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#define IRDMA_RCV_WND_NO_FC 65536
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#define IRDMA_RCV_WND_FC 65536
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#define IRDMA_CWND_NO_FC 0x1
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#define IRDMA_CWND_FC 0x18
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#define IRDMA_ACKCREDS_NO_FC 0x02
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#define IRDMA_ACKCREDS_FC 0x06
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static void
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irdma_check_flow_ctrl(struct irdma_sc_vsi *vsi, u8 user_prio, u8 traffic_class)
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{
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struct irdma_config_check *cfg_chk = &vsi->cfg_check[user_prio];
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if (!irdma_is_config_ok(cfg_chk, vsi)) {
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if (vsi->tc_print_warning[traffic_class]) {
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irdma_pr_info("INFO: Flow control is disabled for this traffic class (%d) on this vsi.\n", traffic_class);
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vsi->tc_print_warning[traffic_class] = false;
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}
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} else {
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if (vsi->tc_print_warning[traffic_class]) {
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irdma_pr_info("INFO: Flow control is enabled for this traffic class (%d) on this vsi.\n", traffic_class);
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vsi->tc_print_warning[traffic_class] = false;
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}
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}
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}
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void
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irdma_check_fc_for_tc_update(struct irdma_sc_vsi *vsi,
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struct irdma_l2params *l2params)
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{
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u8 i;
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for (i = 0; i < IRDMA_MAX_TRAFFIC_CLASS; i++)
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vsi->tc_print_warning[i] = true;
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for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) {
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struct irdma_config_check *cfg_chk = &vsi->cfg_check[i];
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u8 tc = l2params->up2tc[i];
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cfg_chk->traffic_class = tc;
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cfg_chk->qs_handle = vsi->qos[i].qs_handle;
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irdma_check_flow_ctrl(vsi, i, tc);
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}
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}
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void
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irdma_check_fc_for_qp(struct irdma_sc_vsi *vsi, struct irdma_sc_qp *sc_qp)
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{
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u8 i;
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for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) {
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struct irdma_config_check *cfg_chk = &vsi->cfg_check[i];
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irdma_init_config_check(cfg_chk,
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vsi->qos[i].traffic_class,
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vsi->qos[i].qs_handle);
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if (sc_qp->qs_handle == cfg_chk->qs_handle)
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irdma_check_flow_ctrl(vsi, i, cfg_chk->traffic_class);
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}
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|
}
|
|
|
|
#define GLPE_WQMTXIDXADDR 0x50E000
|
|
#define GLPE_WQMTXIDXDATA 0x50E004
|
|
|
|
void
|
|
disable_prefetch(struct irdma_hw *hw)
|
|
{
|
|
u32 wqm_data;
|
|
|
|
wr32(hw, GLPE_WQMTXIDXADDR, 0x12);
|
|
irdma_mb();
|
|
|
|
wqm_data = rd32(hw, GLPE_WQMTXIDXDATA);
|
|
wqm_data &= ~(1);
|
|
wr32(hw, GLPE_WQMTXIDXDATA, wqm_data);
|
|
}
|
|
|
|
void
|
|
disable_tx_spad(struct irdma_hw *hw)
|
|
{
|
|
u32 wqm_data;
|
|
|
|
wr32(hw, GLPE_WQMTXIDXADDR, 0x12);
|
|
irdma_mb();
|
|
|
|
wqm_data = rd32(hw, GLPE_WQMTXIDXDATA);
|
|
wqm_data &= ~(1 << 3);
|
|
wr32(hw, GLPE_WQMTXIDXDATA, wqm_data);
|
|
}
|
|
|
|
#define GL_RDPU_CNTRL 0x52054
|
|
void
|
|
rdpu_ackreqpmthresh(struct irdma_hw *hw)
|
|
{
|
|
u32 val;
|
|
|
|
val = rd32(hw, GL_RDPU_CNTRL);
|
|
val &= ~(0x3f << 10);
|
|
val |= (3 << 10);
|
|
wr32(hw, GL_RDPU_CNTRL, val);
|
|
}
|