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f785676f2a
all of the features in the current working draft of the upcoming C++ standard, provisionally named C++1y. The code generator's performance is greatly increased, and the loop auto-vectorizer is now enabled at -Os and -O2 in addition to -O3. The PowerPC backend has made several major improvements to code generation quality and compile time, and the X86, SPARC, ARM32, Aarch64 and SystemZ backends have all seen major feature work. Release notes for llvm and clang can be found here: <http://llvm.org/releases/3.4/docs/ReleaseNotes.html> <http://llvm.org/releases/3.4/tools/clang/docs/ReleaseNotes.html> MFC after: 1 month
93 lines
2.3 KiB
C++
93 lines
2.3 KiB
C++
//===-- ARMFeatures.h - Checks for ARM instruction features ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the code shared between ARM CodeGen and ARM MC
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//
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//===----------------------------------------------------------------------===//
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#ifndef TARGET_ARM_FEATURES_H
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#define TARGET_ARM_FEATURES_H
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#include "ARM.h"
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namespace llvm {
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template<typename InstrType> // could be MachineInstr or MCInst
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inline bool isV8EligibleForIT(InstrType *Instr, int BLXOperandIndex = 0) {
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switch (Instr->getOpcode()) {
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default:
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return false;
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case ARM::tADC:
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case ARM::tADDi3:
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case ARM::tADDi8:
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case ARM::tADDrSPi:
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case ARM::tADDrr:
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case ARM::tAND:
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case ARM::tASRri:
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case ARM::tASRrr:
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case ARM::tBIC:
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case ARM::tCMNz:
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case ARM::tCMPi8:
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case ARM::tCMPr:
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case ARM::tEOR:
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case ARM::tLDRBi:
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case ARM::tLDRBr:
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case ARM::tLDRHi:
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case ARM::tLDRHr:
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case ARM::tLDRSB:
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case ARM::tLDRSH:
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case ARM::tLDRi:
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case ARM::tLDRr:
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case ARM::tLDRspi:
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case ARM::tLSLri:
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case ARM::tLSLrr:
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case ARM::tLSRri:
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case ARM::tLSRrr:
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case ARM::tMOVi8:
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case ARM::tMUL:
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case ARM::tMVN:
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case ARM::tORR:
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case ARM::tROR:
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case ARM::tRSB:
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case ARM::tSBC:
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case ARM::tSTRBi:
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case ARM::tSTRBr:
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case ARM::tSTRHi:
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case ARM::tSTRHr:
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case ARM::tSTRi:
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case ARM::tSTRr:
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case ARM::tSTRspi:
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case ARM::tSUBi3:
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case ARM::tSUBi8:
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case ARM::tSUBrr:
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case ARM::tTST:
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return true;
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// there are some "conditionally deprecated" opcodes
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case ARM::tADDspr:
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return Instr->getOperand(2).getReg() != ARM::PC;
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// ADD PC, SP and BLX PC were always unpredictable,
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// now on top of it they're deprecated
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case ARM::tADDrSP:
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case ARM::tBX:
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return Instr->getOperand(0).getReg() != ARM::PC;
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case ARM::tBLXr:
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return Instr->getOperand(BLXOperandIndex).getReg() != ARM::PC;
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case ARM::tADDhirr:
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return Instr->getOperand(0).getReg() != ARM::PC &&
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Instr->getOperand(2).getReg() != ARM::PC;
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case ARM::tCMPhir:
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case ARM::tMOVr:
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return Instr->getOperand(0).getReg() != ARM::PC &&
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Instr->getOperand(1).getReg() != ARM::PC;
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}
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}
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}
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#endif
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