mirror of
https://github.com/opnsense/src.git
synced 2026-04-22 23:02:02 -04:00
For the Exception Syndrome Register, ESR_ELx, the upper 32b were previously unused, but now may contain additional exception info as of Armv8.7 (FEAT_LS64). Extend ESR from u32->u64 in exception handling code to support this. In addition, also extend Saved Program Status Register SPSR_ELx in the same way to allow for future extensions. Reviewed by: andrew Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D38983 |
||
|---|---|---|
| .. | ||
| acpica | ||
| arm64 | ||
| broadcom | ||
| cavium | ||
| conf | ||
| coresight | ||
| freescale/imx | ||
| include | ||
| intel | ||
| iommu | ||
| linux | ||
| nvidia/tegra210 | ||
| qoriq | ||
| qualcomm | ||
| rockchip | ||