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266b0663c5
Overview: Intel(R) QuickAssist Technology (Intel(R) QAT) provides hardware acceleration for offloading security, authentication and compression services from the CPU, thus significantly increasing the performance and efficiency of standard platform solutions. This commit introduces: - Intel® 4xxx Series VF driver support. - Device configurability via sysctls. - UIO support for Intel® 4xxx Series devices. Patch co-authored by: Krzysztof Zdziarski <krzysztofx.zdziarski@intel.com> Patch co-authored by: Michal Gulbicki <michalx.gulbicki@intel.com> Patch co-authored by: Julian Grajkowski <julianx.grajkowski@intel.com> Patch co-authored by: Piotr Kasierski <piotrx.kasierski@intel.com> Patch co-authored by: Lukasz Kolodzinski <lukaszx.kolodzinski@intel.com> Patch co-authored by: Karol Grzadziel <karolx.grzadziel@intel.com> Sponsored by: Intel Corporation Differential Revision: https://reviews.freebsd.org/D39850
196 lines
8.9 KiB
C
196 lines
8.9 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/* Copyright(c) 2021 Intel Corporation */
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/* $FreeBSD$ */
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#ifndef ADF_GEN2_HW_DATA_H_
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#define ADF_GEN2_HW_DATA_H_
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#include "adf_accel_devices.h"
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#include "adf_cfg_common.h"
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/* Transport access */
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#define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
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#define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
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#define ADF_RING_CSR_RING_CONFIG 0x000
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#define ADF_RING_CSR_RING_LBASE 0x040
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#define ADF_RING_CSR_RING_UBASE 0x080
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#define ADF_RING_CSR_RING_HEAD 0x0C0
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#define ADF_RING_CSR_RING_TAIL 0x100
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#define ADF_RING_CSR_E_STAT 0x14C
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#define ADF_RING_CSR_INT_FLAG 0x170
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#define ADF_RING_CSR_INT_SRCSEL 0x174
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#define ADF_RING_CSR_INT_SRCSEL_2 0x178
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#define ADF_RING_CSR_INT_COL_EN 0x17C
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#define ADF_RING_CSR_INT_COL_CTL 0x180
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#define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
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#define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
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#define ADF_RING_CSR_ADDR_OFFSET 0x0
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#define ADF_RING_BUNDLE_SIZE 0x1000
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#define ADF_GEN2_RX_RINGS_OFFSET 8
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#define ADF_GEN2_TX_RINGS_MASK 0xFF
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#define BUILD_RING_BASE_ADDR(addr, size) \
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(((addr) >> 6) & (GENMASK_ULL(63, 0) << (size)))
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#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
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ADF_CSR_RD(csr_base_addr, \
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(ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_HEAD + \
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((ring) << 2))
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#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
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ADF_CSR_RD(csr_base_addr, \
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(ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_TAIL + \
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((ring) << 2))
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#define READ_CSR_E_STAT(csr_base_addr, bank) \
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ADF_CSR_RD(csr_base_addr, \
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(ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_E_STAT)
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#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
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ADF_CSR_WR(csr_base_addr, \
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(ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_RING_CONFIG + ((ring) << 2), \
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value)
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static inline uint64_t
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read_base(struct resource *csr_base_addr, u32 bank, u32 ring)
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{
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u32 l_base, u_base;
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u64 addr;
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l_base = ADF_CSR_RD(csr_base_addr,
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(ADF_RING_BUNDLE_SIZE * bank) +
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ADF_RING_CSR_RING_LBASE + (ring << 2));
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u_base = ADF_CSR_RD(csr_base_addr,
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(ADF_RING_BUNDLE_SIZE * bank) +
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ADF_RING_CSR_RING_UBASE + (ring << 2));
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addr = (uint64_t)l_base & 0x00000000FFFFFFFFULL;
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addr |= (uint64_t)u_base << 32 & 0xFFFFFFFF00000000ULL;
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return addr;
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}
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#define READ_CSR_RING_BASE(csr_base_addr, bank, ring) \
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read_base(csr_base_addr, bank, ring)
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#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
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do { \
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u32 l_base = 0, u_base = 0; \
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l_base = (u32)((value)&0xFFFFFFFF); \
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u_base = (u32)(((value)&0xFFFFFFFF00000000ULL) >> 32); \
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ADF_CSR_WR(csr_base_addr, \
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(ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_RING_LBASE + ((ring) << 2), \
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l_base); \
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ADF_CSR_WR(csr_base_addr, \
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(ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_RING_UBASE + ((ring) << 2), \
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u_base); \
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} while (0)
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#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
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ADF_CSR_WR(csr_base_addr, \
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(ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_HEAD + \
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((ring) << 2), \
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value)
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#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
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ADF_CSR_WR(csr_base_addr, \
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(ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_TAIL + \
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((ring) << 2), \
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value)
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#define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \
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ADF_CSR_WR(csr_base_addr, \
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(ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_INT_FLAG, \
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value)
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#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
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do { \
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ADF_CSR_WR(csr_base_addr, \
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(ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_INT_SRCSEL, \
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ADF_BANK_INT_SRC_SEL_MASK_0); \
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ADF_CSR_WR(csr_base_addr, \
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(ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_INT_SRCSEL_2, \
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ADF_BANK_INT_SRC_SEL_MASK_X); \
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} while (0)
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#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
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ADF_CSR_WR(csr_base_addr, \
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(ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_INT_COL_EN, \
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value)
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#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
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ADF_CSR_WR(csr_base_addr, \
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(ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_INT_COL_CTL, \
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ADF_RING_CSR_INT_COL_CTL_ENABLE | (value))
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#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
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ADF_CSR_WR(csr_base_addr, \
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(ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_INT_FLAG_AND_COL, \
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value)
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/* AE to function map */
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#define AE2FUNCTION_MAP_A_OFFSET (0x3A400 + 0x190)
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#define AE2FUNCTION_MAP_B_OFFSET (0x3A400 + 0x310)
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#define AE2FUNCTION_MAP_REG_SIZE 4
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#define AE2FUNCTION_MAP_VALID BIT(7)
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#define READ_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index) \
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ADF_CSR_RD(pmisc_bar_addr, \
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AE2FUNCTION_MAP_A_OFFSET + \
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AE2FUNCTION_MAP_REG_SIZE * (index))
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#define WRITE_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index, value) \
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ADF_CSR_WR(pmisc_bar_addr, \
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AE2FUNCTION_MAP_A_OFFSET + \
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AE2FUNCTION_MAP_REG_SIZE * (index), \
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value)
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#define READ_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index) \
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ADF_CSR_RD(pmisc_bar_addr, \
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AE2FUNCTION_MAP_B_OFFSET + \
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AE2FUNCTION_MAP_REG_SIZE * (index))
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#define WRITE_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index, value) \
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ADF_CSR_WR(pmisc_bar_addr, \
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AE2FUNCTION_MAP_B_OFFSET + \
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AE2FUNCTION_MAP_REG_SIZE * (index), \
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value)
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/* Admin Interface Offsets */
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#define ADF_ADMINMSGUR_OFFSET (0x3A000 + 0x574)
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#define ADF_ADMINMSGLR_OFFSET (0x3A000 + 0x578)
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#define ADF_MAILBOX_BASE_OFFSET 0x20970
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/* Arbiter configuration */
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#define ADF_ARB_OFFSET 0x30000
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#define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180
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#define ADF_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0))
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#define ADF_ARB_REG_SLOT 0x1000
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#define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
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#define READ_CSR_RING_SRV_ARB_EN(csr_addr, index) \
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ADF_CSR_RD(csr_addr, \
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ADF_ARB_RINGSRVARBEN_OFFSET + (ADF_ARB_REG_SLOT * (index)))
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#define WRITE_CSR_RING_SRV_ARB_EN(csr_addr, index, value) \
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ADF_CSR_WR(csr_addr, \
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ADF_ARB_RINGSRVARBEN_OFFSET + (ADF_ARB_REG_SLOT * (index)), \
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value)
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/* Power gating */
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#define ADF_POWERGATE_DC BIT(23)
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#define ADF_POWERGATE_PKE BIT(24)
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/* Default ring mapping */
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#define ADF_GEN2_DEFAULT_RING_TO_SRV_MAP \
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(CRYPTO << ADF_CFG_SERV_RING_PAIR_0_SHIFT | \
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CRYPTO << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \
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UNUSED << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \
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COMP << ADF_CFG_SERV_RING_PAIR_3_SHIFT)
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/* Error detection and correction */
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#define ADF_GEN2_AE_CTX_ENABLES(i) ((i)*0x1000 + 0x20818)
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#define ADF_GEN2_AE_MISC_CONTROL(i) ((i)*0x1000 + 0x20960)
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#define ADF_GEN2_ENABLE_AE_ECC_ERR BIT(28)
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#define ADF_GEN2_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
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#define ADF_GEN2_UERRSSMSH(i) ((i)*0x4000 + 0x18)
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#define ADF_GEN2_CERRSSMSH(i) ((i)*0x4000 + 0x10)
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#define ADF_GEN2_ERRSSMSH_EN BIT(3)
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#define ADF_NUM_HB_CNT_PER_AE (ADF_NUM_THREADS_PER_AE + ADF_NUM_PKE_STRAND)
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void adf_gen2_init_hw_csr_info(struct adf_hw_csr_info *csr_info);
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#endif
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