John Baldwin d141141610 Opt for performance over power-saving on Intel CPUs that have a ... P-state but not C-state invariant TSC by changing the default behavior to leaving the TSC enabled as the timecounter and disabling C2+ instead of disabling the TSC by default. Discussed with: jkim Tested by: Jan Kokemuller <jan.kokemueller@gmail.com>		2015-01-29 20:41:42 +00:00
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acpica	Create a cpuset mask for each NUMA domain that is available in the	2015-01-08 15:53:13 +00:00
bios	Add missing header needed by free(9).	2012-09-30 15:42:20 +00:00
cpufreq	Pull in r267961 and r267973 again. Fix for issues reported will follow.	2014-06-28 03:56:17 +00:00
include	Update Features2 to display SDBG capability of processor. This is	2015-01-08 16:50:35 +00:00
iommu	Right now, for non-coherent DMARs, page table update code flushes the	2015-01-11 20:27:15 +00:00
isa	Include mca_machdep.h.	2015-01-18 03:43:47 +00:00
pci	Pull in r267961 and r267973 again. Fix for issues reported will follow.	2014-06-28 03:56:17 +00:00
x86	Opt for performance over power-saving on Intel CPUs that have a	2015-01-29 20:41:42 +00:00
xen	loader: fix the size of MODINFOMD_MODULEP	2015-01-20 12:28:24 +00:00