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825b7c222a
On several systems we've noticed that when NTB link goes down, the Physical Layer User Test Pattern registers we use as additional scratchpad registers (that is explicitly allowed by the chip specs) become read-only for about 100us. I see no explanation for this in the chip specs, neither why it was not seen before, may be a race. Since we do need these registers, workaround it by repeating writes until we succeed or 1ms timeout expire. MFC after: 1 week (cherry picked from commit 3883c6fbf232452098ba6ea802ef1426d83d2d68) |
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| .. | ||
| if_ntb | ||
| ntb_hw | ||
| test | ||
| ntb.c | ||
| ntb.h | ||
| ntb_if.m | ||
| ntb_transport.c | ||
| ntb_transport.h | ||