Michal Meloun a89156f53f ARM: Use new ARMv6 naming conventions for cache and TLB functions ... in all but ARMv4 specific files. Expand ARMv6 compatibility stubs in cpu-v4.h. Use physical address in L2 cache functions if ARM_L2_PIPT is defined.		2016-02-05 14:57:41 +00:00
..
imx	ARM: Use new ARMv6 naming conventions for cache and TLB functions	2016-02-05 14:57:41 +00:00
vybrid	EHCI: Make core reset and port speed reading more generic.	2016-01-28 14:11:59 +00:00
fsl_ocotp.c	The ocotp driver provides access to registers containing chip configuration	2014-09-02 02:54:55 +00:00
fsl_ocotpreg.h	Make it possible to access the ocotp registers before the ocotp device	2014-02-16 03:09:39 +00:00
fsl_ocotpvar.h	It turns out Freescale cleverly made the ocotp device compatible across	2014-02-15 21:21:57 +00:00