Juli Mallett 70019a0be7 o) Cavium Octeon doesn't need nop barriers. ... o) Have mips_wblush just do syncw, not sync on Cavium Octeon. o) Add support for reading and writing some Octeon-specific registers. NB: Some of these are not entirely Octeon-specific. Submitted by: Bhanu Prakash		2011-02-06 22:21:18 +00:00
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adm5120	- dump_avail layout should be sequence of [start, end)	2010-12-09 07:47:40 +00:00
alchemy	- dump_avail layout should be sequence of [start, end)	2010-12-09 07:47:40 +00:00
atheros	Add missing ar91xx definition for the WMAC reset control.	2011-01-09 06:17:46 +00:00
cavium	If there is no WQE available for a packet that needs segmentation, drop it	2011-01-20 23:51:03 +00:00
compile
conf	Use simplified ldscripts rather than specific ones	2011-01-20 19:17:05 +00:00
idt	- dump_avail layout should be sequence of [start, end)	2010-12-09 07:47:40 +00:00
include	o) Cavium Octeon doesn't need nop barriers.	2011-02-06 22:21:18 +00:00
malta	- dump_avail layout should be sequence of [start, end)	2010-12-09 07:47:40 +00:00
mips	Put the general logic for being a CPU hog into a new function	2011-02-02 16:35:10 +00:00
rmi	Move 'cpu CPU_RMI' to std.xlr, this is common for all XLR cpus.	2011-01-20 12:45:29 +00:00
sentry5	- dump_avail layout should be sequence of [start, end)	2010-12-09 07:47:40 +00:00
sibyte	- dump_avail layout should be sequence of [start, end)	2010-12-09 07:47:40 +00:00