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opnsense-src/sys/riscv/htif
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Ruslan Bukin fd3dc9f439 Add memory barriers (fence instructions) so the data wrotten by hardware 
to physical address now can be read by VA.

This fixes operation on Rocket Core (FPGA).

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-04-22 15:12:05 +00:00
..
htif.c Add support for symmetric multiprocessing (SMP). 2016-02-24 16:50:34 +00:00
htif.h
htif_block.c Add memory barriers (fence instructions) so the data wrotten by hardware 2016-04-22 15:12:05 +00:00
htif_console.c Add support for ddb(4). 2016-03-10 15:51:43 +00:00