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231 lines
6.2 KiB
C
231 lines
6.2 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/* Copyright(c) 2007-2022 Intel Corporation */
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#ifndef ADF_CFG_COMMON_H_
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#define ADF_CFG_COMMON_H_
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#include <sys/types.h>
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#include <sys/ioccom.h>
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#include <sys/cpuset.h>
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#define ADF_CFG_MAX_STR_LEN 128
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#define ADF_CFG_MAX_KEY_LEN_IN_BYTES ADF_CFG_MAX_STR_LEN
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/*
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* Max value length increased to 128 to support more length of values.
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* like Dc0CoreAffinity = 0, 1, 2,... config values to max cores
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*/
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#define ADF_CFG_MAX_VAL_LEN_IN_BYTES 128
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#define ADF_CFG_MAX_SECTION_LEN_IN_BYTES ADF_CFG_MAX_STR_LEN
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#define ADF_CFG_NULL_TERM_SIZE 1
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#define ADF_CFG_BASE_DEC 10
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#define ADF_CFG_BASE_HEX 16
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#define ADF_CFG_ALL_DEVICES 0xFFFE
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#define ADF_CFG_NO_DEVICE 0xFFFF
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#define ADF_CFG_AFFINITY_WHATEVER 0xFF
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#define MAX_DEVICE_NAME_SIZE 32
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#define ADF_MAX_DEVICES (32 * 32)
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#define ADF_MAX_ACCELENGINES 12
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#define ADF_CFG_STORAGE_ENABLED 1
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#define ADF_DEVS_ARRAY_SIZE BITS_TO_LONGS(ADF_MAX_DEVICES)
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#define ADF_GEN2_SSM_WDT_PKE_DEFAULT_VALUE 0x3000000
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#define ADF_WDT_TIMER_SYM_COMP_MS 3
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#define ADF_MIN_HB_TIMER_MS 100
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#define ADF_CFG_MAX_NUM_OF_SECTIONS 16
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#define ADF_CFG_MAX_NUM_OF_TOKENS 16
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#define ADF_CFG_MAX_TOKENS_IN_CONFIG 8
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#define ADF_CFG_RESP_POLL 1
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#define ADF_CFG_RESP_EPOLL 2
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#define ADF_CFG_DEF_CY_RING_ASYM_SIZE 64
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#define ADF_CFG_DEF_CY_RING_SYM_SIZE 512
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#define ADF_CFG_DEF_DC_RING_SIZE 512
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#define ADF_CFG_MAX_CORE_NUM 256
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#define ADF_CFG_MAX_TOKENS ADF_CFG_MAX_CORE_NUM
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#define ADF_CFG_MAX_TOKEN_LEN 10
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#define ADF_CFG_ACCEL_DEF_COALES 1
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#define ADF_CFG_ACCEL_DEF_COALES_TIMER 10000
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#define ADF_CFG_ACCEL_DEF_COALES_NUM_MSG 0
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#define ADF_CFG_ASYM_SRV_MASK 1
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#define ADF_CFG_SYM_SRV_MASK 2
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#define ADF_CFG_DC_SRV_MASK 8
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#define ADF_CFG_UNKNOWN_SRV_MASK 0
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#define ADF_CFG_DEF_ASYM_MASK 0x03
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#define ADF_CFG_MAX_SERVICES 4
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#define ADF_MAX_SERVICES 3
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enum adf_svc_type {
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ADF_SVC_ASYM = 0,
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ADF_SVC_SYM = 1,
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ADF_SVC_DC = 2,
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ADF_SVC_NONE = 3
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};
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struct adf_pci_address {
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unsigned char bus;
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unsigned char dev;
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unsigned char func;
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} __packed;
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#define ADF_CFG_SERV_RING_PAIR_0_SHIFT 0
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#define ADF_CFG_SERV_RING_PAIR_1_SHIFT 3
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#define ADF_CFG_SERV_RING_PAIR_2_SHIFT 6
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#define ADF_CFG_SERV_RING_PAIR_3_SHIFT 9
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enum adf_cfg_service_type { NA = 0, CRYPTO, COMP, SYM, ASYM, USED };
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enum adf_cfg_bundle_type { FREE, KERNEL, USER };
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enum adf_cfg_val_type { ADF_DEC, ADF_HEX, ADF_STR };
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enum adf_device_type {
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DEV_UNKNOWN = 0,
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DEV_DH895XCC,
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DEV_DH895XCCVF,
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DEV_C62X,
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DEV_C62XVF,
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DEV_C3XXX,
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DEV_C3XXXVF,
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DEV_200XX,
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DEV_200XXVF,
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DEV_C4XXX,
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DEV_C4XXXVF,
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DEV_D15XX,
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DEV_D15XXVF,
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DEV_4XXX,
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DEV_4XXXVF
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};
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enum adf_cfg_fw_image_type {
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ADF_FW_IMAGE_DEFAULT = 0,
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ADF_FW_IMAGE_CRYPTO,
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ADF_FW_IMAGE_COMPRESSION,
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ADF_FW_IMAGE_CUSTOM1
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};
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struct adf_dev_status_info {
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enum adf_device_type type;
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uint16_t accel_id;
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uint16_t instance_id;
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uint8_t num_ae;
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uint8_t num_accel;
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uint8_t num_logical_accel;
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uint8_t banks_per_accel;
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uint8_t state;
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uint8_t bus;
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uint8_t dev;
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uint8_t fun;
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int domain;
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char name[MAX_DEVICE_NAME_SIZE];
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u8 sku;
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u32 node_id;
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u32 device_mem_available;
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u32 pci_device_id;
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};
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struct adf_cfg_device {
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/* contains all the bundles info */
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struct adf_cfg_bundle **bundles;
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/* contains all the instances info */
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struct adf_cfg_instance **instances;
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int bundle_num;
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int instance_index;
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char name[ADF_CFG_MAX_STR_LEN];
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int dev_id;
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int max_kernel_bundle_nr;
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u16 total_num_inst;
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};
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enum adf_accel_serv_type {
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ADF_ACCEL_SERV_NA = 0x0,
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ADF_ACCEL_SERV_ASYM,
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ADF_ACCEL_SERV_SYM,
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ADF_ACCEL_SERV_RND,
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ADF_ACCEL_SERV_DC
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};
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struct adf_cfg_ring {
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u8 mode : 1;
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enum adf_accel_serv_type serv_type;
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u8 number : 4;
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};
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struct adf_cfg_bundle {
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/* Section(s) name this bundle is shared by */
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char **sections;
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int max_section;
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int section_index;
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int number;
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enum adf_cfg_bundle_type type;
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cpuset_t affinity_mask;
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int polling_mode;
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int instance_num;
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int num_of_rings;
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/* contains all the info about rings */
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struct adf_cfg_ring **rings;
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u16 in_use;
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u16 max_cfg_svc_num;
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};
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struct adf_cfg_instance {
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enum adf_cfg_service_type stype;
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char name[ADF_CFG_MAX_STR_LEN];
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int polling_mode;
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cpuset_t affinity_mask;
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/* rings within an instance for services */
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int asym_tx;
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int asym_rx;
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int sym_tx;
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int sym_rx;
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int dc_tx;
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int dc_rx;
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int bundle;
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};
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#define ADF_CFG_MAX_CORE_NUM 256
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#define ADF_CFG_MAX_TOKENS_IN_CONFIG 8
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#define ADF_CFG_MAX_TOKEN_LEN 10
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#define ADF_CFG_MAX_TOKENS ADF_CFG_MAX_CORE_NUM
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#define ADF_CFG_ACCEL_DEF_COALES 1
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#define ADF_CFG_ACCEL_DEF_COALES_TIMER 10000
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#define ADF_CFG_ACCEL_DEF_COALES_NUM_MSG 0
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#define ADF_CFG_RESP_EPOLL 2
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#define ADF_CFG_SERV_RING_PAIR_1_SHIFT 3
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#define ADF_CFG_SERV_RING_PAIR_2_SHIFT 6
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#define ADF_CFG_SERV_RING_PAIR_3_SHIFT 9
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#define ADF_CFG_RESP_POLL 1
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#define ADF_CFG_ASYM_SRV_MASK 1
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#define ADF_CFG_SYM_SRV_MASK 2
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#define ADF_CFG_DC_SRV_MASK 8
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#define ADF_CFG_UNKNOWN_SRV_MASK 0
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#define ADF_CFG_DEF_ASYM_MASK 0x03
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#define ADF_CFG_MAX_SERVICES 4
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#define ADF_CTL_IOC_MAGIC 'a'
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#define IOCTL_STATUS_ACCEL_DEV \
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_IOWR(ADF_CTL_IOC_MAGIC, 3, struct adf_dev_status_info)
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#define IOCTL_RESERVE_RING \
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_IOWR(ADF_CTL_IOC_MAGIC, 10, struct adf_user_reserve_ring)
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#define IOCTL_RELEASE_RING \
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_IOWR(ADF_CTL_IOC_MAGIC, 11, struct adf_user_reserve_ring)
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#define IOCTL_ENABLE_RING \
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_IOWR(ADF_CTL_IOC_MAGIC, 12, struct adf_user_reserve_ring)
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#define IOCTL_DISABLE_RING \
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_IOWR(ADF_CTL_IOC_MAGIC, 13, struct adf_user_reserve_ring)
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#define IOCTL_GET_NUM_DEVICES _IOR(ADF_CTL_IOC_MAGIC, 4, int32_t)
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#define ADF_CFG_HB_DEFAULT_VALUE 500
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#define ADF_CFG_HB_COUNT_THRESHOLD 3
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#define ADF_MIN_HB_TIMER_MS 100
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#define IOCTL_GET_CFG_VAL \
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_IOW(ADF_CTL_IOC_MAGIC, 5, struct adf_user_cfg_ctl_data)
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enum adf_device_heartbeat_status {
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DEV_HB_UNRESPONSIVE = 0,
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DEV_HB_ALIVE,
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DEV_HB_UNSUPPORTED
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};
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struct adf_dev_heartbeat_status_ctl {
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uint16_t device_id;
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enum adf_device_heartbeat_status status;
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};
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#define IOCTL_HEARTBEAT_ACCEL_DEV \
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_IOWR(ADF_CTL_IOC_MAGIC, 9, struct adf_dev_heartbeat_status_ctl)
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#endif
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