Make that distinction more explicit and regular in the code.
The difference in behavior is documented in the respective datasheets.
Previously, the code handled the distinction by writing the control
register multiple times where at least one write was zero and another
was one.
This can be considered a follow-up to r363021.
Reviewed by: manu
MFC after: 4 weeks
Differential Revision: https://reviews.freebsd.org/D26308
wakeup() does not have any effect on pause(), so if a transfer was
not finished by the time of the first check, then the thread
would sleep full 30 ms.
To do: protect the transfer and interrupt code with the mutex,
switch from tsleep from msleep
Reviewed by: manu
MFC after: 3 weeks
Differential Revision: https://reviews.freebsd.org/D26309
Every revision of twsi after the A20 have a bug where we need to
write again the control register after each interrupts. We also need
to add some delay before writing to this register, a simple read of the
same register does the job so do that.
Also fix the case when we have finish sending all the bytes, it only worked
for 1 byte transfer (the same kind that we do for talking to the PMIC on A20
boards).
While here add more debug messages and rework some of them.
This was tested by talking to a AT23C32 eeprom and a DS3231 RTC from an
H3 and A20 board.
PR: 247576
Reported by: Manuel Stühn (freebsd@justmail.de)
MFC after: 1 week
We use to handle each message separately in i2c_transfer but that cannot
work with message with NOSTOP as it confuses the controller that we disable
the interrupts and start a new message.
Handle every message in the interrupt handler and fire a new start condition
if the previous message have NOSTOP, the controller understand this as a
repeated start.
This fixes booting on Allwinner A10/A20 platform where before the i2c controller
used to write 0 to the PMIC register that control the regulators as it though that
this was the continuation of the write message.
Tested on: A20 BananaPi, Cubieboard 1 (kevans)
Reported by: kevans
MFC after: 1 month
Instead of precalculating the different speed, respect the bus frequency
and calculate the clock register parameter based on it.
If the platform didn't register the core clk, fallback on the precomputed
values (This is likely do be the case on Marvell boards).
Add the ability to use interrupts for i2c message.
We still use polling for early boot i2c transfer (for PMIC
for example) but as soon as interrupts are available use them.
On Allwinner SoC >A20 is seems that polling mode is broken for some
reason, this is now fixed by using interrupt mode.
For Allwinner also fix the frequency calculation, the one in the code
was for when the APB frequency is at 48Mhz while it is at 24Mhz on most
(all?) Allwinner SoCs. We now support both cases.
While here add more debug info when it's compiled in.
Tested On: A20, H3, A64
MFC after: 1 month
being overwritten, they are set only bits (cleared by hardware).
Disable the Acknowledge of the controller slave address. The slave mode is
not supported.
Make sure the interrupt flag bit is being cleared as recommended, add a
delay() _after_ clear the interrupt bit.
Sponsored by: Rubicon Communications, LLC (Netgate)
In some cases, the driver must handle given properties located in
specific OF subnode. Instead of creating duplicate set of function, add
'node' as argument to existing functions, defaulting it to device OF node.
MFC after: 3 weeks
Pressing the PEK (power enable key) will shutdown the board.
Some events are reported to devd via system "PMU" and subsystem
"Battery", "AC" and "USB" such as connected/disconnected.
Some sensors values (power source voltage/current) are reported via
sysctl (dev.axp209_pmu.X.)
It also expose a gpioc node usable in kernel and userland. Only 3 of
the 4 GPIO are exposed (The GPIO3 is different and mostly unused on
boards). Most popular boards uses GPIO1 as a sense pin for OTG power.
Add a dtsi file that adds gpio-controller capability to the device as
upstream doesn't defined it and include it in our custom DTS.
Reviewed by: jmcneill
Approved by: cognet (mentor)
Differential Revision: https://reviews.freebsd.org/D6135
support for the i2c, mmc, and gmac clocks. Further clocks can be added as
needed.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Reviewed by: jmcneill
Differential Revision: https://reviews.freebsd.org/D5339
Marvell twsi part, however uses different register locations, as such split
the existing driver into Marvell and Allwinner attachments.
While here clean a few style issues.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Differential Revision: https://reviews.freebsd.org/D4846
